Adddp/Subdp Instructions 6; Adddp/Subdp Instruction Phases; Adddp/Subdp Execution - Texas Instruments TMS320C6000 Series Reference Manual

6.3.14 ADDDP/SUBDP Instructions
Table 6–29. ADDDP/SUBDP Execution
Figure 6–22. ADDDP/SUBDP Instruction Phases
PG PS
The ADDDP/SUBDP instructions use the E1 through E7 phases of the pipeline
to complete their operations (see Table 6–29). The lower 32 bits of the result
are written on E6, and the upper 32 bits of the result are written on E7. The
ADDDP/SUBDP instructions are executed on the .L unit. The functional unit
latency for ADDDP/SUBDP instructions is 2. The status is written to the
FADCR on E6. Figure 6–22 shows the pipeline phases the ADDDP/SUBDP
instructions use.
Pipeline
Stage E1
Read src1_l
src2_l
Written
Unit in use .L
PW PR DP DC
E2 E3 E4
src1_h
src2_h
.L
E1 E2 E3 E4
6 delay slots
TMS320C67x Pipeline
Functional Unit Hazards
E5 E6 E7
dst_l dst_h
E5 E6 E7
6-49