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Store to Memory With a Register Offset or 5-Bit Unsigned Constant Offset
Table 3–17. Data Types Supported by Stores
Table 3–18. Address Generator Options
Execution
ld/st
Mnemonic
Field
STB
0 1 1 Store byte
STH
1 0 1 Store halfword
STW
1 1 1 Store word
Mode Field
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
Increments and decrements default to 1 and offsets default to zero when no
bracketed register or constant is specified. Stores that do no modification to
the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst 5
offset is left-shifted by 2, 1, or 0 for word, halfword, and byte loads, respectively.
Parentheses, ( ), can be used to set a nonscaled, constant offset. For example,
STW (.unit) *+ baseR (12) dst represents an offset of 12 bytes whereas STW
(.unit) *+ baseR [12] dst represents an offset of 12 words, or 48 bytes. You must
type either brackets or parentheses around the specified offset if you use the
optional offset parameter.
Word and halfword addresses must be aligned on word (two LSBs are 0) and
halfword (LSB is 0) boundaries, respectively.
src
if (cond)
mem
else
nop
Store Data Type
Syntax
*+R[ offsetR ]
*–R[ offsetR ]
*+ +R[ offsetR ]
*– –R[ offsetR ]
*R+ +[ offsetR ]
*R– –[ offsetR ]
*+R[ ucst5 ]
*–R[ ucst5 ]
*+ +R[ ucst5 ]
*– –R[ ucst5 ]
*R+ +[ ucst5 ]
*R– –[ ucst5 ]
TMS320C62x/C67x Fixed-Point Instruction Set
STB/STH/STW
SIze
Left Shift of Offset
8
0 bits
16
1 bit
32
2 bits
Modification Performed
Positive offset
Negative offset
Preincrement
Predecrement
Postincrement
Postdecrement
Positive offset
Negative offset
Preincrement
Predecrement
Postincrement
Postdecrement
3-123
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