Branch Execution Block Diagram - Texas Instruments TMS320C6000 Series Reference Manual

Figure 5–17. Branch Execution Block Diagram
Fetch
STH
SADD
STH
LDW
Decode
32
Execute
MVK
.L1 .S1
Figure 5–17 shows a branch execution block diagram. If a branch is in the E1
phase of the pipeline (in the .S2 unit in the figure), its branch target is in the
fetch packet that is in PG during that same cycle (shaded in the figure).
Because the branch target has to wait until it reaches the E1 phase to begin
execution, the branch takes five delay slots before the branch target code
executes.
STH SADD SADD
SADD SHR SHR
STH SADD SADD
LDW SHR SHR
32 32
SMPYH SMPY
LDW
SMPY
.M1 .D1
Pipeline Execution of Instruction Types
256
SMPYH SMPY
SMPYH SMPYH
SMPYH SMPY
SMPYH SMPYH
32 32 32
SADD SADD
LDW
.D2
SUB B
LDW LDW
SUB B
MV NOP
32 32
B MVK
SMPYH B
.M2 .S2
TMS320C62x Pipeline
PG
PS
PW
PR
DP
DC
E1
.L2
5-17