Address Generator Options - Texas Instruments TMS320C6000 Series Reference Manual

LDDW
Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset
Table 4–10. Address Generator Options
Execution
4-52
The destination register pair must consist of a consecutive even and odd regis-
ter pair from the same register file. The instruction can be used to load a
double-precision floating-point value (64 bits), a pair of single-precision float-
ing-point words (32 bits), or a pair of 32-bit integers. The least significant
32 bits are loaded into the even register and the most significant 32 bits
(containing the sign bit and exponent) are loaded into the next register (which
is always the odd register). The register pair syntax places the odd register
first, followed by a colon, then the even register (that is, A1:A0, B1:B0, A3:A2,
B3:B2, etc.).
All 64 bits of the double-precision floating point value are stored in big- or little-
endian byte order, depending on the mode selected. When LDDW is used to
load two 32-bit single-precision floating-point values or two 32-bit integer val-
ues, the order is dependent on the endian mode used. In little-endian mode,
the first 32-bit word in memory is loaded into the even register. In big-endian
mode, the first 32-bit word in memory is loaded into the odd register. Regard-
less of the endian mode, the double word address must be on a doubleword
boundary (the three LSBs are zero).
Table 4–10 summarizes the address generation options supported.
Mode Field
0 1 0 1
0 1 0 0
1 1 0 1
1 1 0 0
1 1 1 1
1 1 1 0
0 0 0 1
0 0 0 0
1 0 0 1
1 0 0 0
1 0 1 1
1 0 1 0
dst
if (cond) mem
else nop
Syntax
*+R[ offsetR ]
*–R[ offsetR ]
*+ +R[ offsetR ]
*– –R[ offsetR ]
*R+ +[ offsetR ]
*R– –[ offsetR ]
*+R[ ucst5 ]
*–R[ ucst5 ]
*+ +R[ ucst5 ]
*– –R[ ucst5 ]
*R+ +[ ucst5 ]
*R– –[ ucst5 ]
Modification Performed
Positive offset
Negative offset
Preincrement
Predecrement
Postincrement
Postdecrement
Positive offset
Negative offset
Preincrement
Predecrement
Postincrement
Postdecrement