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Table 6–1. Operations Occurring During Floating-Point Pipeline Phases
Stage
Phase
Program
Program
fetch
address
generation
Program
address sent
Program
wait
Program
data receive
Program
Dispatch
decode
Decode
Execute
Execute 1
† This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction
does not write an y results or have any pipeline operation after E1.
Table 6–1 summarizes the pipeline phases and what happens in each.
Symbol
During This Phase
PG
The address of the fetch packet is determined.
PS
The address of the fetch packet is sent to the memory.
PW
A program memory access is performed.
PR
The fetch packet is at the CPU boundary.
DP
The next execute packet of the fetch packet is determined
and sent to the appropriate functional unit to be decoded.
DC
Instructions are decoded in functional units.
E1
For all instruction types, the conditions for the instructions
are evaluated and operands are read.
For load and store instructions, address generation is
performed and address modifications are written to the
†
register file.
For branch instructions, branch fetch packet in PG phase
†
is affected.
For single-cycle instructions, results are written to a regis-
†
ter file.
For DP compare, ADDDP/SUBDP, and MPYDP instruc-
tions, the lower 32-bits of the sources are read. For all oth-
er instructions, the sources are read.
For 2-cycle DP instructions, the lower 32 bits of the result
are written to a register file.
Pipeline Operation Overview
†
†
TMS320C67x Pipeline
Instruction
Type
Completed
Single-cycle
6-7
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