Texas Instruments TMS320C6000 Series Reference Manual page 384

Index
C
circular addressing
block size calculations 2-10
block size specification 3-21
registers that perform 2-9
clearing
an individual interrupt 7-14
interrupts 7-14
clock cycle 5-9, 6-11
CLR instruction 3-48 to 3-50
CMPEQ instruction 3-51 to 3-52
CMPEQDP instruction 4-28 to 4-29
CMPEQSP instruction 4-30 to 4-31
CMPGT instruction 3-53 to 3-55
CMPGTDP instruction 4-32 to 4-33
CMPGTSP instruction 4-34 to 4-35
CMPGTU instruction 3-53 to 3-55
CMPLT instruction 3-56 to 3-58
CMPLTDP instruction 4-36 to 4-37
CMPLTSP instruction 4-38 to 4-39
CMPLTU instruction 3-56 to 3-58
code, definition A-1
conditional operations 3-16
conditional registers 3-16
conflict detectability 3-20
contraints
on crosspaths 3-17
on floatin-point instructions 6-16 to 6-19
on floating-point instructions 4-12 to 4-15
on general-purpose registers 3-19 to 3-21
on instructions using the same functional
unit 3-17
on LDDW instruction 4-14
on loads and stores 3-18
on long data 3-18
on register reads 3-19
on resources 3-17
control
individual interrupts 7-13
of interrupts 7-11
control register
file extension ('C67x) 2-13
interrupt 7-10
list of 2-8
register addresses for accessing 3-87
Index-2
control status register (CSR) 7-10
description 2-8, 2-11
figure 2-11, 7-11
interrupt control fields 7-11
CPU
control register file 2-8
cycle 5-9, 5-11, 6-11, 6-16
data paths
TMS320C62x 2-2
TMS320C67x 2-3
functional units 2-6
general-purpose register files 2-4
introduction 1-8
load and store paths 2-7
TMS320C62x block diagram 5-5
TMS320C67x block diagram 6-5
CPU data paths 2-1
relationship to register files 2-7
TMS320C62x 2-2
TMS320C67x 2-3
CPU ID field (CSR) 2-11
creg opcode field defined 3-16
cross paths 2-7, 3-17
CSR. See control status register (CSR)
D
.D functional unit
load hazard 6-34
store hazard 6-35
LDDW instruction with long write hazard 6-37
single-cycle 6-36
.D functional units 2-6
.D unit hazards
LDDW instruction with long write
instruction 6-37
load instruction 6-34
single-cycle instruction 6-36
store instruction 6-35
DA1 and DA2. See data address paths
data address paths 2-7
data address pointer 5-15, 6-42
data format (IEEE standard) 4-6
data load accesses, versus program memory
accesses 5-22, 6-56
data paths. See CPU data paths
data storage format, 40-bit 2-5
DC pipeline phase 5-4, 6-4