Mpydp Instructions 6; Mpyid Instruction Phases; Mpydp Instruction Phases; Mpydp Execution - Texas Instruments TMS320C6000 Series Reference Manual

Figure 6–24. MPYID Instruction Phases
PG PS PW
6.3.17 MPYDP Instructions
Table 6–32. MPYDP Execution
Figure 6–25. MPYDP Instruction Phases
PG PS PW
PR DP DC E1
The MPYDP instruction uses the E1 through E10 phases of the pipeline to
complete its operations (see Table 6–32). The lower 32 bits of src1 are read
on E1 and E2, and the upper 32 bits of src1 are read on E3 and E4. The lower
32 bits of src2 are read on E1 and E3, and the upper 32 bits of src2 are read
on E2 and E4. The lower 32 bits of the result are written on E9, and the upper
32 bits of the result are written on E10. The MPYDP instruction is executed on
the .M unit. The functional unit latency for the MPYDP instruction is 4. The
status is written to the FMCR on E9. Figure 6–25 shows the pipeline phases
the MPYDP instructions use.
Pipeline
Stage E1
Read src1_l
src2_l
Written
Unit in use .M
PR DP DC E1
E2 E3 E4 E5
9 delay slots
E2 E3 E4
src1_l src1_h src1_h
src2_h src2_l src2_h
.M .M .M
E2 E3 E4 E5
9 delay slots
Functional Unit Hazards
E6 E7 E8 E9
E5 E6 E7 E8
E6 E7 E8 E9
TMS320C67x Pipeline
E10
E9 E10
dst_l dst_h
E10
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