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3.8.3
Syntax for Load/Store Address Generation
Table 3–7. Indirect Address Generation for Load/Store
Addressing Type
Register indirect
Register relative
Register relative with
15-bit constant offset
Base + index
The 'C62x and 'C67x CPUs have a load/store architecture, which means that
the only way to access data in memory is with a load or store instruction.
Table 3–7 shows the syntax of an indirect address to a memory location.
Sometimes a large offset is required for a load/store. In this case you can use
the B14 or B15 register as the base register, and use a 15-bit constant ( ucst15 )
as the offset.
No Modification of
Address Register
*R
*+R[ ucst5 ]
*–R[ ucst5 ]
*+B14/B15[ ucst15 ]
*+R[ offsetR ]
*–R[ offsetR ]
Preincrement or
Predecrement of
Address Register
*++R
*– –R
*+ +R[ ucst5 ]
*– –R[ ucst5 ]
not supported
*++R[ offsetR ]
*– –R[ offsetR ]
TMS320C62x/C67x Fixed-Point Instruction Set
Addressing Modes
Postincrement or
Postdecrement of
Address Register
*R++
*R– –
*R+ +[ ucst5 ]
*R– –[ ucst5 ]
not supported
*R+ +[ offsetR ]
*R– –[ offsetR ]
3-23
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