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5.1.3
Execute
Figure 5–4. Execute Phases of the Pipeline and Functional Block Diagram of the
TMS320C62x
(a)
E1
E2
E3
(b)
Execute
SADD
B
.L1
.S1
15
14
13
12 11
10
9
Register file A
32
Data address 1
The execute portion of the fixed-point pipeline is subdivided into five phases
(E1–E5). Different types of instructions require different numbers of these
phases to complete their execution. These phases of the pipeline play an im-
portant role in your understanding the device state at CPU cycle boundaries.
The execution of different types of instructions in the pipeline is described in
section 5.2, Pipeline Execution of Instruction Types . Figure 5–4(a) shows the
execute phases of the pipeline in sequential order from left to right.
Figure 5–4(b) shows the portion of the functional block diagram in which
execution occurs.
E4
E5
SMPY
STH
.M1
.D1
8 7
6
5 4
3
2
1
0
Data 1
32
Data memory interface control
16
0
1
2
8
9
Internal data memory
(byte addressable)
E1
STH
SMPYH
.D2
32
15
14
13
12
11
32
Data 2
16
16
16
3
4
5
6
7
Pipeline Operation Overview
SADD
SUB
.M2
.S2
10
9
8
7
6
5
4
3
Register file B
Data address 2
TMS320C62x Pipeline
.L2
2
1
0
32
5-5
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