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Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP User Manual

Dsp turbo-decoder coprocessor 2 (tcp2)
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TMS320C6457 DSP
Turbo-Decoder Coprocessor 2 (TCP2)
User's Guide
Literature Number: SPRUGK1
March 2009

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  Summary of Contents for Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP

  • Page 1 TMS320C6457 DSP Turbo-Decoder Coprocessor 2 (TCP2) User's Guide Literature Number: SPRUGK1 March 2009...
  • Page 2 SPRUGK1 – March 2009 Submit Documentation Feedback...
  • Page 3: Table Of Contents

    Preface Features Introduction Overview Standalone (SA) Mode Input Data Format Output Decision Data Format Stopping Criteria Stopping Test Unit Shared-Processing (SP) Mode Input Data Format Output Data Format Registers Peripheral Identification Register (PID) TCP2 Input Configuration Register 0 (TCPIC0) TCP2 Input Configuration Register 1 (TCPIC1) TCP2 Input Configuration Register 2 (TCPIC2) TCP2 Input Configuration Register 3 (TCPIC3) TCP2 Input Configuration Register 4 (TCPIC4)
  • Page 4 Architecture Sub-block and Sliding Window Segmentation Subframe Segmentation (SP mode only) Reliability and Prolog Length Calculation Added Features Programming EDMA3 Resources Programming Standalone (SA) Mode Programming Shared-Processing (SP) Mode Output Parameters Events Generation Debug Mode: Pause After Each Map Errors and Status 13.1 Errors 13.2...
  • Page 5 www.ti.com 3GPP and IS2000 Turbo-Encoder Block Diagram 3GPP and IS2000 Turbo-Decoder Block Diagram TCP2 Block Diagram Standalone (SA) Mode Block Diagram Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4 EN = 1 (Little-Endian Mode) Rate = 1/2 EN = 0 (Big-Endian Mode) Rate = 1/2 EN = 1 (Little-Endian Mode) Rate = 1/3 EN = 0 (Big-Endian Mode) Rate = 1/3 EN = 1 (Little-Endian Mode) Rate = 1/4...
  • Page 6 TCP2 Endian Register (TCPEND) TCP2 Error Register (TCPERR) TCP2 Status Register (TCPSTAT) TCP2 Emulation Register (TCPEMU) Data Source - EDMA3 (Big Endian) Data Destination - Kernel (Little Endian) Data Source - Kernel (Little Endian) Data Destination - EDMA3 (Big Endian) Data Memory EN = 1 (Little-Endian Mode) Rate = 1/2 EN = 0 (Big-Endian Mode) Rate = 1/2...
  • Page 7 www.ti.com Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode Interleaver Data TCP2 Registers TCP2 RAMs Peripheral Identification Register (PID) Field Descriptions TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions TCP2 Input Configuration Register 3 (TCPIC3) TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions...
  • Page 8: Preface

    (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. Trademarks TMS320C6000, C6000, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. Preface Preface SPRUGK1 –...
  • Page 9: Features

    TMS320C6457 Turbo-Decoder Coprocessor 2 Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signal processor (DSPs) of the TMS320C6000E DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards.
  • Page 10: Introduction

    Introduction Introduction Encoding is done as shown in systematic, convolutional (RSC) encoders connected in parallel, with an interleaver (the turbo interleaver) preceding the second recursive convolutional encoder. The two recursive convolutional codes are called the constituent encoders of the turbo code and have a constraint length K = 4. Figure 1.
  • Page 11: Overview

    www.ti.com uses the corresponding estimates from the other decoder as a priori likelihood. The a priori information is seen as beforehand knowledge, meaning that some messages are more likely to occur than others. A posteriori information adds to the a priori information the knowledge gained by the decoding. The uncoded information bits (corrupted by the noisy channel) are available to each decoder to initialize the a priori likelihoods.
  • Page 12: Standalone (Sa) Mode

    Standalone (SA) Mode Turbo-decoder coprocessor (TCP2) Table 1. Frame Sizes for Standalone (SA) Mode and Standalone (SA) Mode In standalone (SA) mode, the DSP sends the systematic and parity data, and the interleaver table. The TCP2 then works independently of the DSP (standalone), iterates a defined maximum number of times, and outputs hard decision data.
  • Page 13: Input Data Format

    www.ti.com One iteration of turbo decoding consists of 2 MAPs processing, the first MAP with the initial switch position (as shown in Figure 4), the second MAP with the other position of the switch. After each MAP, a stopping test can be performed based on the following methods. These tests are user configurable. Comparing the extrinsic SNR estimate to a SNR threshold (user defined) CRC pattern match Max iterations...
  • Page 14: Systematic/Parity Data For Rates 1/2, 1/3, 1/4, 1/5, And

    Standalone (SA) Mode Figure 5. Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and 3/4 63:62 61:56 55:50 49:44 RSVD Figure 6. EN = 1 (Little-Endian Mode) Rate = 1/2 Word N + 1 Word N + 3 Word Word N + 2 Figure 8.
  • Page 15: En = 0 (Big-Endian Mode) Rate

    www.ti.com Word Word N + 2 Figure 12. EN = 1 (Little-Endian Mode) Rate = 1/5 Word N + 1 Word N + 3 Word Word N + 2 Figure 14. EN = 1 (Little-Endian Mode) Rate = 3/4 Word N + 1 Word N + 3...
  • Page 16: Output Decision Data Format

    Standalone (SA) Mode Figure 15. Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 Word Word N + 2 Word N + 4 4.1.2 Interleaver Indexes Each index is a 15-bit value being effectively saved as 16 bits right-justified. Given an index j, an interleaver table t, and a data x, the interleaved data x is given as x' = x[t(j)].
  • Page 17: Stopping Test Unit

    www.ti.com The CRC-based stopping criterion can be used by setting the CRC polynomial length (CRCLEN) and the number of CRC iterations required to pass CRCITERPASS. After each iteration, hard decisions are computed and a CRC is performed. The CRC polynomial is a programmable 32-bit number. To avoid situations where a CRC test passes for a very noisy frame of data, the hard decisions need to pass the CRC test for a number of consecutive iterations, which is user-defined via the CRCITERPASS bit field.
  • Page 18: Shared-Processing (Sp) Mode

    Shared-Processing (SP) Mode The CRC will process one sub-block at time using the data stored from the previous sub-block. The decision bit will be used by a CRC block. After all sub-blocks have been processed, the CRC bits in the CRC block are checked and compared with the last crc_length bits of the frame.
  • Page 19: Shared-Processing (Sp) Mode Block Diagram

    www.ti.com Figure 16. Shared-Processing (SP) Mode Block Diagram The shared-processing mode allows the DSP/TCP2 system to support frames strictly larger than 20730. The DSP breaks the large frame into 2 or more smaller frames of 20480 or less. Each frame is called a subframe.
  • Page 20: Subframe Equations

    Shared-Processing (SP) Mode Size while Size if ( Size if ( Size 1st sub−frame: Prolog header is transferred by EDMA3, but not used by the TCP: The TCP EDMA3 I/F unit reads and counts this data but does not store it into the coprocessor memory. Actually, the TCP is using the frame header symbols and does not need any header prolog computation.
  • Page 21 www.ti.com Each sub-frame is independent of each other. There are three types of sub-frames. The first sub-frame starts the trellis from the zero state. The last sub-frame ends the trellis from a known state. The remaining middle subframes do not start or end from a known state. The EDMA3 transfers ACNT*BCNT number of bytes in A-Sync Mode and ACNT*BCNT*CCNT number of bytes in AB-Sync Mode.
  • Page 22: Input Data Format

    Shared-Processing (SP) Mode Figure 19. TCP2 Shared Processing Block Diagram MAP 1: De−interlaced (Apriori 2) or MAP 2: Interleaved (Apriori 1) Input Data Format 5.1.1 Systematic and Parity Data The original systematic and parity data is organized as described in the data for MAP0 and MAP1 as shown in the following figures.
  • Page 23: En = 1 (Little-Endian Mode) Rate

    www.ti.com Figure 23. EN = 1 (Little-Endian Mode) Rate = 1/3 Word N + 1 Word N + 3 Word Word N + 2 Figure 25. EN = 1 (Little-Endian Mode) Rate = 1/4 Word N + 1 Word N + 3 Word Word N + 2...
  • Page 24: Output Data Format

    Shared-Processing (SP) Mode Word Word N + 2 Figure 29. EN = 1 (Little-Endian Mode) Rate = 3/4 Word N + 1 Word N + 3 Word N + 5 Figure 30. Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 Word Word N + 2...
  • Page 25: Registers

    www.ti.com Registers The TCP2 contains several memory-mapped registers accessible via the CPU, QDMA, and EDMA3. A peripheral-bus access is faster than an EDMA3-bus access for isolated accesses (typically when accessing control registers). EDMA3-bus accesses are intended to be used for EDMA3 transfers and are meant to provide maximum throughput to/from the TCP2.
  • Page 26 Registers TCP2 Data Offset Register/Memory Address Abbreviation 0xA0000 0xB0000 TMS320C6457 Turbo-Decoder Coprocessor 2 Table 4. TCP2 RAMs (continued) Name Beta Prolog Memory Alpha Prolog Memory www.ti.com Address Range Length 0xa0000-0xa0FFF 0x00000280 0xb0000-0xb0FFF 0x00000280 SPRUGK1 – March 2009 Submit Documentation Feedback...
  • Page 27: Peripheral Identification Register (Pid)

    www.ti.com Peripheral Identification Register (PID) The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. All bits within this register are read-only (writes have no effect) meaning that the values within this register should be hard-coded with the appropriate values and must not change from their reset state.
  • Page 28: Tcp2 Input Configuration Register 0 (Tcpic0)

    Registers TCP2 Input Configuration Register 0 (TCPIC0) The TCP2 input configuration register 0 (TCPIC0) is shown in configures the TCP. Figure 33. TCP2 Input Configuration Register 0 (TCPIC0) Rsvd R/W-0 Reserved NUMSW OUTF R/W-0 R/W-0 R/W-0 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6.
  • Page 29: Tcp2 Input Configuration Register 1 (Tcpic1)

    www.ti.com TCP2 Input Configuration Register 1 (TCPIC1) The TCP2 input configuration register 1 (TCPIC1) is shown in configures the TCP. Figure 34. TCP2 Input Configuration Register 1 (TCPIC1) 23 22 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7.
  • Page 30: Tcp2 Input Configuration Register 3 (Tcpic3)

    Registers TCP2 Input Configuration Register 3 (TCPIC3) The TCP2 input configuration register 3 (TCPIC3) is shown in informs the TCP2 on the EDMA3 data flow segmentation. Figure 36. TCP2 Input Configuration Register 3 (TCPIC3) Reserved Reserved ORDER R/W-0 R/W-0 R/W-0 MINITER R/W-0 LEGEND: R/W = Read/Write;...
  • Page 31: Tcp2 Input Configuration Register 4 (Tcpic4)

    www.ti.com TCP2 Input Configuration Register 4 (TCPIC4) The TCP2 input configuration register 4 (TCPIC4) is shown in TCPIC4 informs the TCP2 on the EDMA3 data flow segmentation. Figure 37. TCP2 Input Configuration Register 4 (TCPIC4) Reserved CRCITERPASS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10.
  • Page 32: Tcp2 Input Configuration Register 5 (Tcpic5)

    Registers TCP2 Input Configuration Register 5 (TCPIC5) The TCP2 input configuration register 5 (TCPIC5) is shown in TCPIC5 provides the 32-bit CRC Polynomial to TCP2. Figure 38. TCP2 Input Configuration Register 5 (TCPIC5) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11.
  • Page 33: Tcp2 Input Configuration Register 6 (Tcpic6)

    www.ti.com TCP2 Input Configuration Register 6 (TCPIC6) The TCP2 input configuration register 6 (TCPIC6) is shown in TCPIC6 sets the tail bits used by the TCP. Figure 39. TCP2 Input Configuration Register 6 (TCPIC6) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13.
  • Page 34: Tcp2 Input Configuration Register 7 (Tcpic7)

    Registers 6.10 TCP2 Input Configuration Register 7 (TCPIC7) The TCP2 input configuration register 7 (TCPIC7) is shown in TCPIC7 sets set the tail bits used by the TCP. Figure 40. TCP2 Input Configuration Register 7 (TCPIC7) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
  • Page 35: Tcp2 Input Configuration Register 8 (Tcpic8)

    www.ti.com 6.11 TCP2 Input Configuration Register 8 (TCPIC8) The TCP2 input configuration register 8 (TCPIC8) is shown in TCPIC8 sets the tail bits used by the TCP. Figure 41. TCP2 Input Configuration Register 8 (TCPIC8) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15.
  • Page 36: Tcp2 Input Configuration Register 9 (Tcpic9)

    Registers 6.12 TCP2 Input Configuration Register 9 (TCPIC9) The TCP2 input configuration register 9 (TCPIC9) is shown in TCPIC9 sets the tail bits used by the TCP. Figure 42. CP2 Input Configuration Register 9 (TCPIC9) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16.
  • Page 37: Tcp2 Input Configuration Register 10 (Tcpic10)

    www.ti.com 6.13 TCP2 Input Configuration Register 10 (TCPIC10) The TCP2 input configuration register 10 (TCPIC10) is shown in TCPIC10 sets the tail bits used by the TCP. Figure 43. TCP2 Input Configuration Register 10 (TCPIC10) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17.
  • Page 38: Tcp2 Input Configuration Register 11 (Tcpic11)

    Registers Figure 44. TCP2 Input Configuration Register 11 (TCPIC11) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. TCP2 Input Configuration Register 11 (TCPIC11) Field Descriptions Field Value 31-18 Reserved 17-0 TAIL6 0-FFFF FFFFh CDMA-2000 Tail Symbol Pattern for Code Rate 1/5 tail+2...
  • Page 39: Tcp2 Input Configuration Register 12 (Tcpic12)

    www.ti.com 6.15 TCP2 Input Configuration Register 12 (TCPIC12) The TCP2 input configuration register 12 (TCPIC12) is shown in Figure 45. TCP2 Input Configuration Register 12 (TCPIC12) 24 23 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19.
  • Page 40: Tcp2 Input Configuration Register 14 (Tcpic14)

    Registers 6.17 TCP2 Input Configuration Register 14 (TCPIC14) The TCP2 input configuration register 14 (TCPIC14) is shown in Figure 47. TCP2 Input Configuration Register 14 (TCPIC14) 24 23 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21.
  • Page 41: Tcp2 Input Configuration Register 15 (Tcpic15)

    www.ti.com 6.18 TCP2 Input Configuration Register 15 (TCPIC15) The TCP2 input configuration register 15 (TCPIC15) is shown in Figure 48. TCP2 Input Configuration Register 15 (TCPIC15) 24 23 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.
  • Page 42: Tcp2 Output Parameter Register 0 (Tcpout0)

    Registers 6.19 TCP2 Output Parameter Register 0 (TCPOUT0) The TCP2 output parameter register 0 (TCPOUT0) is shown in Figure 49. TCP2 Output Parameter Register 0 (TCPOUT0) 29 28 24 23 Reserved FINAL_ITER Reserved R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24.
  • Page 43: Tcp2 Output Parameter Register 2 (Tcpout2)

    www.ti.com 6.21 TCP2 Output Parameter Register 2 (TCPOUT2) The TCP2 output parameter register 2 (TCPOUT2) is shown in Figure 51. TCP2 Output Parameter Register 2 (TCPOUT2) CNT_RE_MAP1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26.
  • Page 44: Tcp2 Endian Register (Tcpend)

    Registers 6.23 TCP2 Endian Register (TCPEND) The TCP2 endian register (TCPEND) is shown in only be used when the DSP is set to big-endian mode. LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. TCP2 Endian Register (TCPEND) Field Descriptions Field Value Description...
  • Page 45: Tcp2 Error Register (Tcperr)

    www.ti.com 6.24 TCP2 Error Register (TCPERR) The TCP2 error register (TCPERR) is shown in the coprocessor sends an interrupt to the C6457 CPU. The following errors are feedback in the error word. Reserved MINTER Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29.
  • Page 46 Registers Table 29. TCP2 Error Register (TCPERR) Field Descriptions (continued) Field Value Description Subframe length. No error Subframe length > 5114 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Prolog length.
  • Page 47: Tcp2 Status Register (Tcpstat)

    www.ti.com 6.25 TCP2 Status Register (TCPSTAT) The TCP2 status register (TCPSTAT) is shown in Reserved CRC_PASS SNR_EXCEED ACTIVE_STATE REXT LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions Field Value Description...
  • Page 48 Registers Table 30. TCP2 Status Register (TCPSTAT) Field Descriptions (continued) Field Value Description REXT Defines if the TCP2 is waiting for extrinsic memory 0 data to be read. Not waiting Waiting for RAM extrinsic memory 0 to be read Defines if the TCP2 is waiting for a extrinsic memory 1 data to be written. Not waiting Waiting for RAM extrinsic memory 1 to be loaded Defines if the TCP2 is waiting for systematic and parity data to be written.
  • Page 49: Tcp2 Emulation Register (Tcpemu)

    www.ti.com 6.26 TCP2 Emulation Register (TCPEMU) In emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emulation mode. Emulation support helps in system debug. Emulation modes are achieved with the programmable SOFT and FREE bits in the TCP2 Emulation Register (TCPEMU) at the configuration bus address 0x00070.
  • Page 50: Endianness

    Endianness The TCP2 is halted (or paused) after processing the ongoing frame. Any current frame processing must complete. Sync vents for the new frame will be hold until TCP_EMUSUSP is released. The TCP2 is restarted from the paused state and begins the next frame operations. In TCP_STATE = 14, the TCP_EMUSUSP will have no effect.
  • Page 51: Data Memory

    www.ti.com 63:62 61:56 55:50 49:44 RSVD Figure 62. EN = 1 (Little-Endian Mode) Rate = 1/2 Word N + 1 Word N + 3 Word Word N + 2 Figure 64. EN = 1 (Little-Endian Mode) Rate = 1/3 Word N + 1 Word N + 3...
  • Page 52: En = 1 (Little-Endian Mode) Rate = 1/5

    Endianness Word Word N + 2 Figure 68. EN = 1 (Little-Endian Mode) Rate = 1/5 Word N + 1 Word N + 3 Word Word N + 2 Figure 70. EN = 1 (Little-Endian Mode) Rate = 3/4 Word N + 1 Word N + 3...
  • Page 53: Source Of Endianness Manager - Ordering Of Hard Decisions In 32-Bit Word (Out_Order = 0)

    www.ti.com Word Word N + 2 Word N + 4 7.1.1 Hard Decision Data 1. OUT_ORDER = 0 EN = 1 (Little-Endian Mode) OUT_ORDER = 0 results in ordering the hard decision data from 0 to 31 in the 32-bit word output. Figure 72.
  • Page 54: Destination Of Endianness Manager (Out_Order = 0)

    Endianness Figure 77. Destination of Endianness Manager (OUT_ORDER = 0) Stage Stage N - 32 N - 33 4. OUT_ORDER = 1 EN = 1 (Little-Endian Mode) Figure 78. Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) Stage Stage N - 1...
  • Page 55: Tcp_Endian Register

    www.ti.com LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Data Native Format Interleaver Indexes 16 bits (15 bits right justified) Extrinsic Data 8 bits (7 bits right justified 7.1.3 Interleaver Data Little_big_endian 7.1.3.1 ENDIAN_INTR = 1 If ENDIAN_INTR = 1, data are saved in their native format (16 bits) in the DSP (see SPRUGK1 –...
  • Page 56: Interleaver Indexes In Dsp Memory (Endian_Intr = 1)

    Endianness Figure 83. Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1) Endian_Intr=1 Memory Base 0 INTER0 Base 2 INTER1 Base 4 INTER2 Base 6 INTER3 They have to be swapped as described in Figure 84. Data Source - EDMA3 (ENDIAN_INTR = 1) INTER0 Figure 85.
  • Page 57: Data Source - Edma3 (Endian_Intr = 0)

    www.ti.com Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0) INTER1 Figure 88. Data Destination - Kernel (ENDIAN_INTR = 0) INTER3 7.1.4 Extrinsic Data Little_big_endian 7.1.4.1 ENDIAN_EXTR = 1 If ENDIAN_EXTR = 1, data are saved in their native format (8 bits) in the DSP (see Table 38.
  • Page 58: Data Source - Kernel (Endian_Extr = 1)

    Endianness Figure 90. Data Source - Kernel (ENDIAN_EXTR = 1) 63:56 55:48 47:40 EXT7 EXT6 EXT5 Figure 91. Data Destination - EDMA3 (ENDIAN_EXTR = 1) 63:56 55:48 47:40 EXT0 EXT1 EXT2 TMS320C6457 Turbo-Decoder Coprocessor 2 39:32 31:24 23:16 EXT4 EXT3 EXT2 39:32 31:24...
  • Page 59: Architecture

    www.ti.com 7.1.4.2 ENDIAN_EXTR = 0 If ENDIAN_EXTR = 0, data are saved in word format (32 bits) in the DSP (see Table 39. Extrinsic in DSP Memory (ENDIAN_EXTR = Figure 92. Extrinsic in DSP Memory (ENDIAN_EXTR = 0) Endian_Extr=0 Memory Base 0 Base 7 They have to be swapped as described in...
  • Page 60: Sub-Block And Sliding Window Segmentation

    Architecture Data from memory The TCP2 can enable or disable the max star function by modifying the E_MAX_STAR bit in the TCPIC3 register. E_MAX_STAR = 0 = Enable max star E_MAX_STAR = 1 = Disable max star Log-map algorithm is implemented in a highly paralleled manner using the sliding window principle. The max-log-map algorithm is implemented with apriori scaled prior to the map decoder.
  • Page 61: Subframe Segmentation (Sp Mode Only)

    www.ti.com Figure 96. Sliding Windows and Sub-blocks Segmentation (Example with 5 Sub-blocks, frame length First subblock Prolog Middle subblock Only used in SP mode. in SA mode, start from known state 0 Sliding Window Figure 96 show diagrams for the sliding windows for both alpha and beta. Each sliding window consists of a reliability section and a prolog section.
  • Page 62: Reliability And Prolog Length Calculation

    Architecture Figure 97. Shared Processing Subframe Segmentation (Example with 5 Subframes) First subframe Prolog Must point to valid address Reliability and Prolog Length Calculation F: Frame length (number of bits in a frame prior to turbo-encoding) R: 1/code rate P: Prolog length (number of symbols to be used in the prolog not taking into account the rate) The unit is designed so that reliability size ranges from 40 to 128 bits and prolog size ranges from 4 to 48 bits.
  • Page 63: Added Features

    www.ti.com This computation should be done by the DSP CPU. It should be noted that a 1 must be subtracted from the calculated R value prior to writing to TCPIC1. Note: The reliability length must fill the above properties to receive a correct decoding. If these rules are not followed, the MAP will execute, but the BER might not be optimal.
  • Page 64: Programming

    Programming 8.4.2 Input Sign The TCP assumes that the encoded bits are converted into signed binary symbols using the following mapping: 0 -1, 1 +1 and scaled by -2*a/Σ Many receivers may perform this scaling without applying the -1 factor. With TCP, this requires the DSP to perform the -1 multiplication as the TCP expects this scaling.
  • Page 65: Edma3 Resources

    www.ti.com Note that several user channels can be programmed prior to starting the TCP2. Table 42. EDMA3 Parameters in Standalone (SA) Mode Direction Transmit (DSP TCP) Receive (TCP DSP) Data Transmit Input configuration parameters Transmit Systematics and parities Transmit Interleaver indexes Receive Hard decisions Receive...
  • Page 66: Programming Standalone (Sa) Mode

    Programming Programming Standalone (SA) Mode Table 42 highlights the required EDMA3 resources to perform a standalone (SA) mode decoding. Each set of EDMA3 parameters uses the EDMA3 linking capabilities. programming and Section 9.2.2 flag that a user-channel has just been decoded is left to you. Suggested implementation is to use the EDMA3 interrupt generation capabilities [see the TMS320C6457 DSP Enhanced Direct Memory Access (EDMA3) Controller Reference Guide (SPRUGK6)] and program the EDMA3 to generate an interrupt after the user-channel's last TCPREVT synchronized EDMA3 transfer has completed.
  • Page 67 www.ti.com – TCINTEN = 0 (Transfer complete interrupt is disabled) – TCC = 1 to 63 (Transfer Complete Code) – TCCMODE = 0 (Normal Completion) – FWID = Don't care – STAT = 0 (Entry is updated as normal) – SYNCDIM = 0 (AB-Sync, Each event triggers the transfer of BCNT arrays of ACNT elements.) –...
  • Page 68 Programming SRCBIDX = 0 (Source 2nd Dimension Index) DSTBIDX = 0 (Destination 2nd Dimension Index SRCCIDX = 0 (Source 3rd Dimension Index) DSTCIDX = 0 (Destination 3rd Dimension Index) CCNT = 1 (No of frames in a block) BCNTRLD: Don't care LINK ADDRESS: See cases 1 and 2 below Upon completion, this EDMA3 transfer is linked to one of the following: 1.
  • Page 69 www.ti.com 3. Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be decoded and the OUTF bit is cleared. 9.2.1.5 Output Parameters Transfer This EDMA3 transfer is optional and depends on the OUTF bit in the TCP2 input configuration register 0 (TCPIC0).
  • Page 70: Programming Shared-Processing (Sp) Mode

    Programming The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31) when SNR stopping criteria is used. The INPUTSIGN bit can be enabled or disabled in TCPIC3 (0 = Use channel input data as is, 1 = multiply channel input data by -1).
  • Page 71 www.ti.com 9.3.1 EDMA3 Programming 9.3.1.1 Input Configuration Parameters Transfer This EDMA3 transfer to the input configuration parameters is a 16-word TCPXEVT frame-synchronized transfer. The parameters should be set as: OPTIONS: – ITCCEN = 0 (Intermediate transfer complete chaining is disabled) –...
  • Page 72 Programming Word count = 2 * ceil (frame_length/2) BCNT = (Word count /2) (No of arrays of length ACNT) DESTINATION ADDRESS: TCPSP (5001 0000h) SRCBIDX = 8 (Source 2nd Dimension Index) DSTBIDX = 8 (Destination 2nd Dimension Index) SRCCIDX = 8 (Source 3rd Dimension Index) DSTCIDX = 8 (Destination 3rd Dimension Index) CCNT = 8 (No of frames in a block) BCNTRLD: Don't care...
  • Page 73 www.ti.com 1. The EDMA3 input configuration parameters transfer parameters of the next user-channel MAP, if there is one ready to be decoded. 2. Dummy EDMA3 transfer parameters, if there are no more user channels LOG-MAP ready to be decoded. 9.3.1.4 Extrinsics Transfer This EDMA3 transfer to the extrinsics buffer is a TCPREVT frame-synchronized transfer.
  • Page 74: Output Parameters

    Output Parameters The EMAXSTR bit can be enabled or disabled in TCPIC3, 0 = max star disabled (enable Max Log-MAP, 1 = max star enabled (enable log MAP)). The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overall system performance (minimum iterations 1 to 31).
  • Page 75: Debug Mode: Pause After Each Map

    www.ti.com Figure 101. TCP2 Events Generation in Shared-Processing (SP) Mode MAP1 TCPXEVT TCPXEVT TCPREVT Input config Syst&Par Extrinsics params TCP processing TCPXEVT TCPXEVT TCPXEVT Input config Syst&Par Apriori params TCP processing MAP 1.2 Debug Mode: Pause After Each Map The TCPEXE register starts, resets, and places TCP2 into debug mode. Writing the following to TCPEXE will place TCP2 into the defined modes.
  • Page 76 Errors and Status 13.1.2 Unexpected Frame Length: F The F bit is set to 1 if the programmed frame length is strictly smaller than 40 or is strictly greater than 20730 for standalone mode. The F bit is set to 1 if the programmed frame length has the following values for shared processing mode: 1.
  • Page 77: 13.2 Status

    www.ti.com 13.1.10 Unexpected Max and Min Iterations: MAXMINITER The MAXMINITER bit is set to 1 if the minimum iterations are greater than the maximum iterations. 13.2 Status The TCP2 status register (TCPSTAT) reflects the state of the TCP2. 13.2.1 TCP2 Decoder Status: dec_busy The dec_busy is set to 0 if the MAP decoder is in state 0.
  • Page 78 Errors and Status 13.2.12 TCP2 Active State Status: Active_state The Active_state indicates active MAP decoder state. 13.2.13 TCP2 Active Iteration Status: Active_iter The Active_iter indicates active TCP2 iteration. 13.2.14 TCP2 SNR Status: snr_exceed The snr_exceed indicates failed or passed MAPs with respect to SNR. 13.2.15 TCP2 CRC Status: Crc_pass The Crc_pass bit is set to 1 when the CRC has passed.
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