Tms320C62X Nonreset Interrupt Detection And Processing: Pipeline Operation - Texas Instruments TMS320C6000 Series Reference Manual

Figure 7–12. TMS320C62x Nonreset Interrupt Detection and Processing:
Pipeline Operation
Clock cycle 0 1
External INTm
at pin
IFm
IACK
0 0
INUM
Execute packet
n
DC E1
n+1
DP DC
n+2
PR
DP
n+3
PW PR
n+4
PS
PW
n+5
PS
PG
n+6
PG
n+7
n+8
n+9
n+10
n+11
ISFP
CPU cycle
0 1
† IFm is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of INTm.
‡ After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are
disabled when GIE = 0.
GIE = 1
NMIE = 1
The five previous execute packets (n through n + 4) do not contain a
branch (even if the branch is not taken) and are not in the delay slots of
a branch.
Any pending interrupt will be taken as soon as pending branches are
completed.
2 3 4 5 6
{
0 0 0 0 0
E2 E3 E4 E5
E1 E2 E3 E4 E5
DC E1 E2 E3 E4
DP DC E1 E2 E3
PR DP DC E1 E2
PW PR DP DC E1
PS PW PR DP DC
PG PS PW PR DP
PG PS PW PR
PG PS PW
PG PS
PG
2 3 4 5 6
Interrupt Detection and Processing
7 8 9 10 11
m 0 0 0 0
Contains no branch
E5
E4 E5
E3
E4 E5
Annulled Instructions
Cycles 6 – 12: Nonreset
interrupt processing is
disabled.
PG PS PW PR DP
7 8 9 10 11
12 13 14 15 16
0 0 0 0 0
}
DC E1 E2 E3 E4
12 13 14 15 16
Interrupts
17
0
E5
17
7-19