Introduction - Texas Instruments TMS320C6000 Series Reference Manual

The TMS320C6x generation of digital signal processors is part of the TMS320
family of digital signal processors (DSPs). The TMS320C62x devices are
fixed-point DSPs in the TMS320C6x generation, and the TMS320C67x
devices are floating-point DSPs in the TMS320C6x generation. The
TMS320C62x and TMS320C67x are code compatible and both use the
VelociTI architecture, a high-performance, advanced VLIW (very long
instruction word) architecture, making these DSPs excellent choices for multi-
channel and multifunction applications.
The VelociTI architecture of the 'C62x and 'C67x make them the first off-the-
shelf DSPs to use advanced VLIW to achieve high performance through
increased instruction-level parallelism. A traditional VLIW architecture
consists of multiple execution units running in parallel, performing multiple
instructions during a single clock cycle. Parallelism is the key to extremely high
performance, taking these DSPs well beyond the performance capabilities of
traditional superscalar designs. VelociTI is a highly deterministic architecture,
having few restrictions on how or when instructions are fetched, executed, or
stored. It is this architectural flexibility that is key to the breakthrough efficiency
levels of the 'C6x compiler. VelociTI's advanced features include:
Instruction packing: reduced code size
All instructions can operate conditionally: flexibility of code
Variable-width instructions: flexibility of data types
Fully pipelined branches: zero-overhead branching
Topic
1.1 TMS320 Family Overview
1.2 Overview of the TMS320C6x Generation of
Digital Signal Processors
1.3 Features and Options of the TMS320C62x/C67x
1.4 TMS320C62x/C67x Architecture

Introduction

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Chapter 1
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