Single-Cycle Instruction Phases; Single-Cycle Execution Block Diagram; Multiply Instruction Phases - Texas Instruments TMS320C6000 Series Reference Manual

Pipeline Execution of Instruction Types
5.2.1 Single-Cycle Instructions
Figure 5–8. Single-Cycle Instruction Phases
Figure 5–9. Single-Cycle Execution Block Diagram
5.2.2 Multiply Instructions
Figure 5–10. Multiply Instruction Phases
5-12
Single-cycle instructions complete execution during the E1 phase of the pipe-
line. Figure 5–8 shows the fetch, decode, and execute phases of the pipeline
that single-cycle instructions use.
PG
Figure 5–9 shows the single-cycle execution diagram. The operands are read,
the operation is performed, and the results are written to a register, all during
E1. Single-cycle instructions have no delay slots.
Operands
(data)
Multiply instructions use both the E1 and E2 phases of the pipeline to complete
their operations. Figure 5–10 shows the pipeline phases the multiply instruc-
tions use.
PG PS PW
PS PW PR DP
Functional
unit
.L, .S, .M,
or .D
Write results
Register file
PR DP DC
DC E1
E1
1 delay slot
E1 E2