Summary Of Pipeline Operation 6; Fixed-Point Pipeline Phases; Pipeline Operation: One Execute Packet Per Fetch Packet - Texas Instruments TMS320C6000 Series Reference Manual

Pipeline Operation Overview
5.1.4 Summary of Pipeline Operation
Figure 5–5. Fixed-Point Pipeline Phases
Figure 5–6. Pipeline Operation: One Execute Packet per Fetch Packet
Fetch
1 2
packet
n
PG PS
n+1
PG
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
5-6
Figure 5–5 shows all the phases in each stage of the 'C62x pipeline in sequen-
tial order, from left to right.
Fetch
PG PS PW
Figure 5–6 shows an example of the pipeline flow of consecutive fetch packets
that contain eight parallel instructions. In this case, where the pipeline is full,
all instructions in a fetch packet are in parallel and split into one execute packet
per fetch packet. The fetch packets flow in lockstep fashion through each
phase of the pipeline.
For example, examine cycle 7 in Figure 5–6. When the instructions from FP n
reach E1, the instructions in the execute packet from FPn +1 are being
decoded. FP n + 2 is in dispatch while FPs n + 3, n + 4, n + 5, and n + 6 are
each in one of four phases of program fetch. See section 5.3, Performance
Considerations , on page 5-18 for additional detail on code flowing through the
pipeline.
Clock cycle
3 4 5
PW PR DP
PS PW PR
PG PS PW
PG PS
PG
Decode
PR DP DC
6 7 8
DC E1 E2
DP DC E1
PR DP DC
PW PR DP
PS PW PR
PG PS PW
PG PS
PG
Execute
E1 E2 E3 E4
9 10 11
E3 E4 E5
E2 E3 E4
E1 E2 E3
DC E1 E2
DP DC E1
PR DP DC
PW PR DP
PS PW PR
PG PS PW
PG PS
PG
E5
12 13
E5
E4 E5
E3 E4
E2 E3
E1 E2
DC E1
DP DC
PR DP
PW PR
PS PW