Load Instructions; Load Instruction Phases; Load Execution - Texas Instruments TMS320C6000 Series Reference Manual

Functional Unit Hazards
6.3.8

Load Instructions

Table 6–23. Load Execution
Figure 6–14. Load Instruction Phases
6-42
Data loads require five of the pipeline execute phases to complete their opera-
tions (see Table 6–23). Figure 6–14 shows the pipeline phases the load
instructions use.
Pipeline
E1
Stage
Read baseR
offsetR
Written baseR
Unit in use .D
PG PS PW
Figure 6–15 shows the operations occurring in the pipeline phases for a load.
In the E1 phase, the data address pointer is modified in its register. In the E2
phase, the data address is sent to data memory. In the E3 phase, a memory
read at that address is performed.
E2 E3
PR DP DC E1
E4 E5
dst
E2 E3 E4 E5
4 delay slots