Texas Instruments TMS320C6000 Series Reference Manual page 62

Example 3–3. Partially Serial p -Bit Pattern in a Fetch Packet
31 0 31
0
Instruction Instruction
A B
3.5.1 Example Parallel Code
3.5.2 Branching Into the Middle of an Execute Packet
This p- bit pattern:
0 31 0 31
0 1
Instruction Instruction
C D
results in this execution sequence:
Cycle/Execute
Packet
1
2
3
4
Note: Instructions C, D, and E do not use any of the same functional units, cross paths, or
other data path resources. This is also true for instructions F, G, and H.
The || characters signify that an instruction is to execute in parallel with the pre-
vious instruction. The code for the fetch packet in Example 3–3 would be rep-
resented as this:
instruction A
instruction B
instruction C
|| instruction D
|| instruction E
instruction F
|| instruction G
|| instruction H
If a branch into the middle of an execute packet occurs, all instructions at lower
addresses are ignored. In Example 3–3, if a branch to the address containing
instruction D occurs, then only D and E execute. Even though instruction C is
in the same execute packet, it is ignored. Instructions A and B are also ignored
because they are in earlier execute packets. If your result depends on execut-
ing A,B, or C, the branch to the middle of the execute packet will produce an
erroneous result.
0 31 0 31
1 0
Instruction Instruction
E F
Instructions
A
B
C D
F G
TMS320C62x/C67x Fixed-Point Instruction Set
Parallel Operations
0 31 0 31
1 1
Instruction Instruction
G H
E
H
0
0
3-15