Storage Scheme For 40-Bit Data In A Register Pair - Texas Instruments TMS320C6000 Series Reference Manual

Figure 2–3. Storage Scheme for 40-Bit Data in a Register Pair
Figure 2–3 illustrates the register storage scheme for 40-bit long data. Opera-
tions requiring a long input ignore the 24 MSBs of the odd register. Operations
producing a long result zero-fill the 24 MSBs of the odd register. The even
register is encoded in the opcode.
Odd register
31
Ignored
Odd register
Í Í Í Í Í Í Í Í Í
Zero-filled
Í Í Í Í Í Í Í Í Í
General-Purpose Register Files
8 7
0 31
Read from registers
39 32 31
Write to registers
39 32 31
CPU Data Paths and Control
Even register
40-bit data
Even register
40-bit data
0
0
0
2-5