Store Instructions; Store Instruction Phases; Store Execution - Texas Instruments TMS320C6000 Series Reference Manual

Functional Unit Hazards
6.3.7

Store Instructions

Table 6–22. Store Execution
Figure 6–12. Store Instruction Phases
6-40
Store instructions require phases E1 through E3 to complete their operations
(see Table 6–22). Figure 6–12 shows the pipeline phases the store instruc-
tions use. Figure 6–13 shows the operations occurring in the pipeline phases
for a store. In the E1 phase, the address of the data to be stored is computed.
In the E2 phase, the data and destination addresses are sent to data memory.
In the E3 phase, a memory write is performed. The address modification is per-
formed in the E1 stage of the pipeline. Even though stores finish their execu-
tion in the E3 phase of the pipeline, they have no delay slots.
Pipeline
Stage E1
Read baseR,
offsetR
src
Written baseR
Unit in use .D2
PG PS
E2
PW PR DP DC
E3
E1 E2 E3