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TMS320C6455
Texas Instruments TMS320C6455 Manuals
Manuals and User Guides for Texas Instruments TMS320C6455. We have
3
Texas Instruments TMS320C6455 manuals available for free PDF download: Manual, User Manual
Texas Instruments TMS320C6455 Manual (257 pages)
Fixed-Point Digital Signal Processor
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.73 MB
Table of Contents
1 Features
1
CTZ/GTZ/ZTZ BGA Package (Bottom View)
2
Description
2
Functional Block Diagram
4
Table of Contents
5
Revision History
6
Device Characteristics
7
CPU (DSP Core) Description
8
Boot Sequence
13
Pin Assignments
16
Signal Groups Description
20
Terminal Functions
26
Development
51
3 Device Configuration
55
Device Configuration at Device Reset
55
Peripheral Configuration at Device Reset
57
Peripheral Selection after Device Reset
58
Device State Control Registers
60
Device Status Register Description
71
JTAG ID (JTAGID) Register Description
73
Pullup/Pulldown Resistors
74
Configuration Examples
74
4 System Interconnect
77
Internal Buses, Bridges, and Switch Fabrics
77
Data Switch Fabric Connections
78
Configuration Switch Fabric
80
Bus Priorities
82
5 C64X+ Megamodule
83
Memory Architecture
83
Memory Protection
85
Bandwidth Management
86
Power-Down Control
87
Megamodule Resets
87
Megamodule Revision
88
Sprs276M - May 2005 - Revised March 2012
88
C64X+ Megamodule Register Descriptions
89
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90
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91
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92
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93
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94
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95
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96
Device Operating Conditions
97
Absolute Maximum Ratings over Operating Case Temperature Range (Unless Otherwise Noted)
97
Recommended Operating Conditions
97
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97
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98
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
99
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99
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100
C64X+ Peripheral Information and Electrical Specifications
101
Parameter Information
101
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102
Recommended Clock and Control Signal Transition Behavior
103
Power Supplies
103
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104
Enhanced Direct Memory Access (EDMA3) Controller
105
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105
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106
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107
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108
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109
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110
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111
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112
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113
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114
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115
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116
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117
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118
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119
Interrupts
120
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120
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121
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122
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123
Reset Controller
124
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125
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126
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127
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128
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129
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130
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131
PLL1 and PLL1 Controller
132
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133
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134
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135
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136
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137
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138
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139
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140
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141
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142
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143
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144
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145
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146
PLL2 and PLL2 Controller
147
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148
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149
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150
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151
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152
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153
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154
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155
DDR2 Memory Controller
156
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157
External Memory Interface a (EMIFA)
158
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159
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160
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161
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162
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163
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164
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165
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166
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167
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168
I2C Peripheral
169
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170
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171
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172
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173
Host-Port Interface (HPI) Peripheral
174
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175
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176
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177
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178
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179
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180
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181
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182
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183
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184
Multichannel Buffered Serial Port (Mcbsp)
185
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185
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186
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188
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189
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190
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191
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192
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193
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194
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195
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196
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197
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198
Ethernet MAC (EMAC)
199
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199
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200
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201
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202
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203
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204
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205
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206
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207
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208
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209
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210
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211
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212
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213
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214
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215
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216
Timers
217
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218
Enhanced Viterbi-Decoder Coprocessor (VCP2)
219
Enhanced Turbo Decoder Coprocessor (TCP2)
220
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221
Peripheral Component Interconnect (PCI)
222
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222
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223
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224
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225
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226
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227
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228
Utopia
229
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229
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230
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231
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232
Serial Rapidio (SRIO) Port
233
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234
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235
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236
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237
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238
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239
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240
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241
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242
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243
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244
General-Purpose Input/Output (GPIO)
245
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246
Emulation Features and Capability
247
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248
8 Mechanical Data
249
Thermal Data
249
Packaging Information
249
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Texas Instruments TMS320C6455 User Manual (148 pages)
DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO)
Brand:
Texas Instruments
| Category:
IP Access Controllers
| Size: 1.02 MB
Table of Contents
Table of Contents
3
Preface
10
Introduction
11
Purpose of the Peripheral
11
Features
11
Functional Block Diagram
12
EMAC and MDIO Block Diagram
12
Industry Standard(S) Compliance Statement
13
EMAC Functional Architecture
14
Clock Control
14
Memory Map
15
System Level Connections
16
Ethernet Configuration with MII Interface
16
Interface Selection Pins
16
EMAC and MDIO Signals for MII Interface
17
Ethernet Configuration with RMII Interface
18
EMAC and MDIO Signals for RMII Interface
19
Ethernet Configuration with GMII Interface
20
EMAC and MDIO Signals for GMII Interface
21
Ethernet Configuration with RGMII Interface
22
EMAC and MDIO Signals for RGMII Interface
23
Ethernet Protocol Overview
24
Ethernet Frame
24
Ethernet Frame Description
24
Programming Interface
26
Basic Descriptor Format
26
Basic Descriptors
26
Typical Descriptor Linked List
27
Transmit Descriptor Format
30
Receive Descriptor Format
33
EMAC Control Module
37
EMAC Control Module Block Diagram
37
Management Data Input/Output (MDIO) Module
38
MDIO Module Block Diagram
39
EMAC Module
43
EMAC Module Block Diagram
43
Media Independent Interfaces
46
2.10 Packet Receive Operation
50
Receive Frame Treatment Summary
53
Middle of Frame Overrun Treatment
54
2.11 Packet Transmit Operation
55
2.12 Receive and Transmit Latency
55
2.13 Transfer Node Priority
56
2.14 Reset Considerations
56
2.15 Initialization
57
2.16 Interrupt Support
60
2.17 Power Management
63
2.18 Emulation Considerations
63
Emulation Control
63
EMAC Control Module Registers
64
Introduction
64
EMAC Control Module Interrupt Control Register (EWCTL)
64
EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions
64
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT)
65
EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions
65
MDIO Registers
66
Introduction
66
Management Data Input/Output (MDIO) Registers
66
MDIO Version Register (VERSION)
67
MDIO Version Register (VERSION) Field Descriptions
67
MDIO Control Register (CONTROL)
68
MDIO Control Register (CONTROL) Field Descriptions
68
PHY Acknowledge Status Register (ALIVE)
69
PHY Acknowledge Status Register (ALIVE) Field Descriptions
69
PHY Link Status Register (LINK)
70
PHY Link Status Register (LINK) Field Descriptions
70
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
71
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
71
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
72
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
72
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
73
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
73
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
74
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
74
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
75
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
75
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
76
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
76
MDIO User Access Register 0 (USERACCESS0)
77
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
77
MDIO User PHY Select Register 0 (USERPHYSEL0)
78
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
78
MDIO User Access Register 1 (USERACCESS1)
79
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
79
MDIO User PHY Select Register 1 (USERPHYSEL1)
80
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
80
EMAC Port Registers
81
Introduction
81
Ethernet Media Access Controller (EMAC) Registers
81
Transmit Identification and Version Register (TXIDVER)
85
Transmit Identification and Version Register (TXIDVER) Field Descriptions
85
Transmit Control Register (TXCONTROL)
86
Transmit Control Register (TXCONTROL) Field Descriptions
86
Transmit Teardown Register (TXTEARDOWN)
87
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
87
Receive Identification and Version Register (RXIDVER)
88
Receive Identification and Version Register (RXIDVER) Field Descriptions
88
Receive Control Register (RXCONTROL)
89
Receive Control Register (RXCONTROL) Field Descriptions
89
Receive Teardown Register (RXTEARDOWN)
90
Receive Teardown Register (RXTEARDOWN) Field Descriptions
90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
91
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
91
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
92
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
92
Transmit Interrupt Mask Set Register (TXINTMASKSET)
93
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
93
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
94
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
94
MAC Input Vector Register (MACINVECTOR)
95
MAC Input Vector Register (MACINVECTOR) Field Descriptions
95
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
96
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
96
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
97
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
97
Receive Interrupt Mask Set Register (RXINTMASKSET)
98
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
98
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
99
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
99
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
100
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
100
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
101
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
101
MAC Interrupt Mask Set Register (MACINTMASKSET)
102
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
102
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
103
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
103
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
104
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions
104
Receive Unicast Enable Set Register (RXUNICASTSET)
106
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
106
Receive Unicast Clear Register (RXUNICASTCLEAR)
107
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
107
Receive Maximum Length Register (RXMAXLEN)
108
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
108
Receive Buffer Offset Register (RXBUFFEROFFSET)
109
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
109
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
110
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
110
Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)
111
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
111
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
111
Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)
112
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
112
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
112
MAC Control Register (MACCONTROL)
113
MAC Control Register (MACCONTROL) Field Descriptions
113
MAC Status Register (MACSTATUS)
115
MAC Status Register (MACSTATUS) Field Descriptions
115
Emulation Control Register (EMCONTROL)
117
Emulation Control Register (EMCONTROL) Field Descriptions
117
FIFO Control Register (FIFOCONTROL)
118
FIFO Control Register (FIFOCONTROL) Field Descriptions
118
MAC Configuration Register (MACCONFIG)
119
MAC Configuration Register (MACCONFIG) Field Descriptions
119
Soft Reset Register (SOFTRESET)
120
Soft Reset Register (SOFTRESET) Field Descriptions
120
MAC Source Address Low Bytes Register (MACSRCADDRLO)
121
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
121
MAC Source Address High Bytes Register (MACSRCADDRHI)
122
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
122
MAC Hash Address Register 1 (MACHASH1)
123
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
123
MAC Hash Address Register 2 (MACHASH2)
124
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
124
Back off Test Register (BOFFTEST)
125
Back off Random Number Generator Test Register (BOFFTEST)
125
Back off Test Register (BOFFTEST) Field Descriptions
125
Transmit Pacing Algorithm Test Register (TPACETEST)
126
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
126
Receive Pause Timer Register (RXPAUSE)
127
Receive Pause Timer Register (RXPAUSE) Field Descriptions
127
Transmit Pause Timer Register (TXPAUSE)
128
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
128
MAC Address Low Bytes Register (MACADDRLO)
129
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
129
MAC Address High Bytes Register (MACADDRHI)
130
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
130
MAC Index Register (MACINDEX)
131
MAC Index Register (MACINDEX) Field Descriptions
131
Transmit Channel 0-7 DMA Head Descriptor Pointer Register (Txnhdp)
132
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
132
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
132
Receive Channel 0-7 DMA Head Descriptor Pointer Register (Rxnhdp)
133
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
133
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
133
Transmit Channel 0-7 Completion Pointer Register (Txncp)
134
Transmit Channel N Completion Pointer Register (Txncp)
134
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
134
Receive Channel 0-7 Completion Pointer Register (Rxncp)
135
Receive Channel N Completion Pointer Register (Rxncp)
135
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
135
5.50 Network Statistics Registers
136
Statistics Register
136
Statistics Register Field Descriptions
136
Appendix A Glossary
145
Physical Layer Definitions
146
Appendix B Revision History
147
Document Revision History
147
Texas Instruments TMS320C6455 User Manual (50 pages)
DSP DDR2 Memory Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.36 MB
Table of Contents
Table of Contents
3
Preface
7
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
10
Device Block Diagram
10
Peripheral Architecture
11
Clock Control
11
Memory Map
11
Signal Descriptions
11
DDR2 Memory Controller Signals
12
DDR2 Memory Controller Signal Descriptions
12
Protocol Description(S)
13
DDR2 SDRAM Commands
13
Truth Table for DDR2 SDRAM Commands
13
DDR2 MRS and EMRS Command
14
Refresh Command
15
ACTV Command
16
DCAB Command
17
DEAC Command
18
DDR2 READ Command
19
Memory Width, Byte Alignment, and Endianness
20
DDR2 WRT Command
20
Addressable Memory Ranges
20
Address Mapping
21
Byte Alignment
21
Bank Configuration Register Fields for Address Mapping
21
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map
23
DDR2 Memory Controller Interface
24
DDR2 SDRAM Column, Row, and Bank Access
24
DDR2 Memory Controller FIFO Description
24
DDR2 Memory Controller FIFO Block Diagram
25
Refresh Scheduling
27
Refresh Urgency Levels
27
Self-Refresh Mode
28
2.10 Reset Considerations
28
2.11 DDR2 SDRAM Memory Initialization
28
Device and DDR2 Memory Controller Reset Relationship
28
DDR2 SDRAM Mode Register Configuration
29
DDR2 SDRAM Extended Mode Register 1 Configuration
29
2.12 Interrupt Support
30
2.13 EDMA Event Support
30
2.14 Emulation Considerations
30
Using the DDR2 Memory Controller
31
Connecting the DDR2 Memory Controller to DDR2 SDRAM
31
Connecting to Two 16-Bit DDR2 SDRAM Devices
32
Connecting to a Single 16-Bit DDR2 SDRAM Device
33
Connecting to Two 8-Bit DDR2 SDRAM Devices
34
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
35
SDCFG Configuration
35
DDR2 Memory Refresh Specification
36
SDRFC Configuration
36
SDTIM1 Configuration
36
SDTIM2 Configuration
37
DMCCTL Configuration
37
DDR2 Memory Controller Registers
38
Module ID and Revision Register (MIDR)
39
Module ID and Revision Register (MIDR) Field Descriptions
39
DDR2 Memory Controller Status Register (DMCSTAT)
40
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
40
SDRAM Configuration Register (SDCFG)
41
SDRAM Configuration Register (SDCFG) Field Descriptions
41
SDRAM Refresh Control Register (SDRFC)
43
SDRAM Refresh Control Register (SDRFC) Field Descriptions
43
SDRAM Timing 1 Register (SDTIM1)
44
SDRAM Timing 1 Register (SDTIM1) Field Descriptions
44
SDRAM Timing 2 Register (SDTIM2)
46
SDRAM Timing 2 Register (SDTIM2) Field Descriptions
46
Burst Priority Register (BPRIO)
47
Burst Priority Register (BPRIO) Field Descriptions
47
DDR2 Memory Controller Control Register (DMCCTL)
48
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
48
Revision History
49
Important Notice
50
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