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Pipeline Operation Overview
6.1 Pipeline Operation Overview
Figure 6–1. Floating-Point Pipeline Stages
Fetch
6.1.1
Fetch
6-2
The pipeline phases are divided into three stages:
Fetch
Decode
Execute
All instructions in the 'C67x instruction set flow through the fetch, decode, and
execute stages of the pipeline. The fetch stage of the pipeline has four phases
for all instructions, and the decode stage has two phases for all instructions.
The execute stage of the pipeline requires a varying number of phases,
depending on the type of instruction. The stages of the 'C67x pipeline are
shown in Figure 6–1.
Decode
The fetch phases of the pipeline are:
PG: Program address generate
PS: Program address send
PW: Program access ready wait
PR: Program fetch packet receive
The 'C67x uses a fetch packet (FP) of eight instructions. All eight of the instruc-
tions proceed through fetch processing together, through the PG, PS, PW, and
PR phases. Figure 6–2(a) shows the fetch phases in sequential order from left
to right. Figure 6–2(b) shows a functional diagram of the flow of instructions
through the fetch phases. During the PG phase, the program address is gener-
ated in the CPU. In the PS phase, the program address is sent to memory. In
the PW phase, a memory read occurs.
Finally, in the PR phase, the fetch packet is received at the CPU. Figure 6–2(c)
shows fetch packets flowing through the phases of the fetch stage of the pipe-
line. In Figure 6–2(c), the first fetch packet (in PR) is made up of four execute
packets, and the second and third fetch packets (in PW and PS) contain two
execute packets each. The last fetch packet (in PG) contains a single execute
packet of eight single-cycle instructions.
Execute
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