Texas Instruments TMS320C6000 Series Reference Manual page 385

DCC field (CSR) 2-11
decode pipeline stage 5-4, 6-4
decoding instructions 5-4, 6-4
delay slots
description 5-11, 6-16
fixed-point instructions 3-12
floating-point instructions 4-11
stores 5-16, 6-43
DEN1,DEN2 fields
FADCR 2-14 to 2-16
FAUCR 2-16 to 2-18
FMCR 2-18 to 2-20
detection of interrupts 7-18
digital signal processors (DSPs) 1-1
direct memory access (DMA) controller 1-9
disabling an individual interrupt 7-14
disabling maskable interrupts globally 7-12
DIV0 fields (FAUCR) 2-16 to 2-18
double-precision data format 4-6
DP compare instructions
.S-unit instruction hazards 6-22
execution 6-48
figure of phases 6-48
pipeline operation 6-48
DP pipeline phase 5-4, 5-19, 6-4, 6-53
DPINT instruction 4-40 to 4-41
DPSP instruction 4-42 to 4-44
DPTRUNC instruction 4-45 to 4-46
E
E1 phase program counter (PCE1) 2-12
E1–E5 (or E10) pipeline phases 6-5
E1–E5 pipeline phases 5-5
EMIF. See external memory interface (EMIF)
EN field (CSR) 2-11
enabling an individual interrupt 7-14
enabling maskable interrupts globally 7-12
execute packet
multicycle NOPs in 5-20, 6-54
parallel operations 3-13
performance considerations ('C67x) 6-52
pipeline operation 5-18
execute phases of the pipeline 5-22, 6-56
figure 5-5, 6-5
execution notations
fixed-point instructions 3-2
floating-point instructions 4-2
execution table
ADDDP/SUBDP 6-49
INTDP 6-48
MPYDP 6-51
MPYI 6-50
MPYID 6-50
EXT instruction 3-59 to 3-61
external memory interface (EMIF) 1-9
EXTU instruction 3-62 to 3-64
F
FADCR. See floating-point adder configuration
register (FADCR)
FAUCR. See floating-point auxiliary configuration
register (FAUCR)
fetch packet (FP) 3-13, 5-18, 6-52, 7-6
fetch phases of the pipeline 5-22
fetch pipeline phase 5-2, 6-56
fetch pipline phase
TMS320C62x 5-3
TMS320C67x 6-2, 6-3
fixed-point instruction set 3-1 to 3-139
flag, interrupt 7-18, 7-22
floating-point instruction constraints 4-12
floating-point instruction set 4-1 to 4-83
floating-point adder configuration register
(FADCR) 2-13, 2-14 to 2-16
floating-point auxiliary configuration register
(FAUCR) 2-13, 2-16 to 2-18
floating-point multiplier configuration register
(FMCR) 2-13, 2-18 to 2-20
floating-point field definitions
double-precision 4-9
single-precision 4-8
floating-point operands
double precision 4-6
single precision 4-6
FMCR. See floating-point multiplier configuration
register (FMCR)
4-cycle instructions
.L-unit instruction hazards 6-31
.M-unit instruction hazards 6-26
execution 6-47
Index
Index-3