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5.2 Pipeline Execution of Instruction Types
Table 5–2. Execution Stage Length Description for Each Instruction Type
Single Cycle
Execution
E1 Compute result
phases
and write to
register
E2
E3
E4
E5
Delay
slots
† See section 5.2.3 and 5.2.4 for more information on execution and delay slots for stores and loads.
‡ See section 5.2.5 for more information on branches.
Notes:
1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false,
the instruction does not write any results or have any pipeline operation after E1.
2) NOP is not shown and has no operation in any of the execution phases.
The pipeline operation of the 'C62x instructions can be categorized into six
instruction types. Five of these are shown in Table 5–2 (NOP is not included
in the table), which is a mapping of operations occurring in each execution
phase for the different instruction types. The delay slots associated with each
instruction type are listed in the bottom row.
Multiply
Read operands
and start
computations
Compute result
and write to
register
0
1
The execution of instructions can be defined in terms of delay slots. A delay
slot is a CPU cycle that occurs after the first execution phase (E1) of an instruc-
tion. Results from instructions with delay slots are not available until the end
of the last delay slot. For example, a multiply instruction has one delay slot,
which means that one CPU cycle elapses before the results of the multiply are
available for use by a subsequent instruction. However, results are available
from other instructions finishing execution during the same CPU cycle in which
the multiply is in a delay slot.
Pipeline Execution of Instruction Types
Instruction Type
Store
Load
Compute
Compute
address
address
Send address
Send address to
and data to
memory
memory
Access memory
Access memory
Send data back
to CPU
Write data into
register
†
0
TMS320C62x Pipeline
Branch
Target code
‡
in PG
†
‡
4
5
5-11
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