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1.3 Features and Options of the TMS320C62x/C67x
The 'C62x devices operate at 200 MHz (5-ns cycle time). The 'C67x devices
operate at 167 MHz (6-ns cycle time). Both DSPs execute up to eight 32-bit
instructions every cycle. The device's core CPU consists of 32 general-
purpose registers of 32-bit word length and eight functional units:
Two multipliers
Six ALUs
The 'C62x/C67x have a complete set of optimized development tools, includ-
ing an efficient C compiler, an assembly optimizer for simplified assembly-
language programming and scheduling, and a Windows
interface for visibility into source code execution characteristics. A hardware
emulation board, compatible with the TI XDS510 emulator interface, is also
available. This tool complies with IEEE Standard 1149.1–1990, IEEE Stan-
dard Test Access Port and Boundary-Scan Architecture.
Features of the 'C62x/C67x include:
Advanced VLIW CPU with eight functional units, including two multipliers
and six arithmetic units
J
Executes up to eight instructions per cycle for up to ten times the
performance of typical DSPs
J
Allows designers to develop highly effective RISC-like code for fast
development time
Instruction packing
J
Gives code size equivalence for eight instructions executed serially or
in parallel
J
Reduces code size, program fetches, and power consumption.
All instructions execute conditionally.
J
Reduces costly branching
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Increases parallelism for higher sustained performance
Code executes as programmed on independent functional units.
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Industry's most efficient C compiler on DSP benchmark suite
J
Industry's first assembly optimizer for fast development and improved
parallelization
8/16/32-bit data support, providing efficient memory support for a variety
of applications
40-bit arithmetic options add extra precision for vocoders and other com-
putationally intensive applications
Features and Options of the TMS320C62x/C67x
based debugger
Introduction
1-5
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