Texas Instruments TMS320C6000 Reference Manual
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Texas Instruments TMS320C6000 Reference Manual

Texas Instruments TMS320C6000 Reference Manual

Dsp multichannel buffered serial port (mcbsp)
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TMS320C6000 DSP
Multichannel Buffered Serial Port (McBSP)
Reference Guide
Literature Number: SPRU580C
March 2004

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Summary of Contents for Texas Instruments TMS320C6000

  • Page 1 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide Literature Number: SPRU580C March 2004...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
  • Page 3 Preface Read This First About This Manual This document describes the operation of the multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 4 TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the TMS320C6000 peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used.

  • Page 5: Table Of Contents

    Contents Contents Features ............... . . McBSP Interface .
  • Page 6 Contents Clocking and Framing Examples ..........4.6.1 Multiphase Frame Example: AC97 .
  • Page 7 Contents 11 Registers ............... . 11.1 Data Receive Register (DRR) .
  • Page 8 Figures Figures McBSP Block Diagram ............Frame and Clock Operation .
  • Page 9 Figures Unexpected Transmit Frame Synchronization Pulse ....... . Companding Flow .
  • Page 10 Tables Enhanced Features on TMS320C6000 McBSP ........

  • Page 11: Features

    Multichannel Buffered Serial Port (McBSP) This document describes the operation of the multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Features The McBSP provides these functions: Full-duplex communication Double-buffered data registers, which allow a continuous data stream...

  • Page 12: Enhanced Features On Tms320C6000 Mcbsp

    Features All C6000 devices have the same McBSP. However, the C621x/C671x and C64x McBSP has additional features and enhancements that are summarized in Table 1. Table 1. Enhanced Features on TMS320C6000 McBSP Features C620x/C670x C621x/C671x McBSP C64x McBSP DX Enabler (DXENA)

  • Page 13: Mcbsp Interface

    McBSP Interface McBSP Interface The McBSP consists of a data path and a control path that connect to external devices. Separate pins for transmission and reception communicate data to these external devices. Four other pins communicate control information (clocking and frame synchronization). The device communicates to the McBSP using 32-bit-wide control registers accessible via the internal peripheral bus.

  • Page 14: Mcbsp Interface Pins

    McBSP Interface Data is communicated to devices interfacing to the McBSP via the data transmit (DX) pin for transmission and via the data receive (DR) pin for reception. Control information (clocking and frame synchronization) is communicated via CLKS, CLKX, CLKR, FSX, and FSR. The C6000 CPU communicates to the McBSP using 32-bit-wide control registers accessible via the internal peripheral bus.

  • Page 15: Mcbsp Overview

    McBSP Overview McBSP Overview As shown in Figure 1, the receive operation is triple-buffered and the transmit operation is double-buffered. Receive data arrives on the DR and is shifted into the RSR. Once a full element (8, 12, 16, 20, 24, or 32 bits) is received, the RSR is copied to the receive buffer register (RBR) only if the RBR is not full.
  • Page 16 McBSP Overview Device reset or McBSP reset: When the McBSP is reset by device reset or McBSP reset, the state machine is reset to its initial state. All counters and status bits are reset. This includes the receive status bits RFULL, RRDY, and RSYNCERR, and the transmit status bits XEMPTY, XRDY, and XSYNCERR.

  • Page 17: Determining Ready Status

    McBSP Overview Determining Ready Status The RRDY and XRDY bits in SPCR indicate the ready state of the McBSP receiver and transmitter, respectively. Writes and reads from the serial port can be synchronized by any of the following methods: Polling RRDY and XRDY bits Using the events sent to the DMA or EDMA controller (REVT and XEVT) Using the interrupts to the CPU (RINT and XINT) that the events generate Reading DRR and writing to DXR affects RRDY and XRDY, respectively.

  • Page 18: Cpu Interrupts: Rint, Xint

    McBSP Overview CPU Interrupts: RINT, XINT The receive interrupt (RINT) and transmit interrupt (XINT) signals inform the CPU of changes to the serial port status. Four options exist for configuring these interrupts. These options are set by the receive/transmit interrupt mode bits (RINTM and XINTM) in SPCR.

  • Page 19: Clocks, Frames, And Data

    Clocks, Frames, and Data Figure 2. Frame and Clock Operation CLK(R/X) FS(R/X) Á Á Á Á Á D(R/X) Á Á Á Á Á Clocks, Frames, and Data The McBSP has several ways of selecting clocking and framing for both the receiver and transmitter.

  • Page 20: Frame And Clock Operation

    Clocks, Frames, and Data Frame and Clock Operation Receive and transmit frame sync pulses (FSR/X), and clocks (CLKR/X), can either be generated internally by the sample rate generator (see section 4.2) or be driven by an external source. The source of frame sync and clock is selected by programming the mode bits, FS(R/X)M and CLK(R/X)M respectively, in PCR.

  • Page 21: Receive Data Clocking

    Clocks, Frames, and Data Similarly, the receiver can reliably sample data that is clocked (by the transmitter) with a rising-edge clock. The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is always sampled on the falling edge of CLKR_int.

  • Page 22: Sample Rate Generator Clocking And Framing

    Clocks, Frames, and Data Sample Rate Generator Clocking and Framing The sample rate generator is composed of a 3-stage clock divider that provides a programmable data clock (CLKG) and framing signal (FSG), as shown in Figure 6. CLKG and FSG are McBSP internal signals that can be programmed to drive receive and/or transmit clocking, CLK(R/X), and framing, FS(R/X).

  • Page 23: Data Clock Generation

    Clocks, Frames, and Data Data Clock Generation When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1), the data clocks (CLK(R/X)) are driven by the internal sample rate generator output clock, CLKG. You can select for the receiver and transmitter from a variety of data bit clocks including: The input clock to the sample rate generator, which can be either the internal clock source or a dedicated external clock source (CLKS).

  • Page 24: Bit Clock Polarity: Clksp

    Clocks, Frames, and Data In the following examples: = sample generator input clock period = sample generator input clock frequency = CLKG period = CLKG frequency The following equation is given above: f /(CLKGDV + 1); therefore, = (CLKGDV + 1) × S Example 1.

  • Page 25: Bit Clock And Frame Synchronization

    Clocks, Frames, and Data 4.3.4 Bit Clock and Frame Synchronization When CLKS is selected to drive the sample rate generator (CLKSM = 0), GSYNC can be used to configure the timing of CLKG relative to CLKS. GSYNC = 1 ensures that the McBSP and the external device to which it is communicating are dividing down the CLKS with the same phase relationship.

  • Page 26: Digital Loopback Mode: Dlb

    Clocks, Frames, and Data Figure 8. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 CLKS (CLKSP = 1) CLKS (CLKSP = 0) FSR external (FSRP = 0) FSR external (FSRP = 1) CLKG (no need to resync) CLKG (needs resync) When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that the following conditions are met:...

  • Page 27: Receive Clock Selection: Dlb, Clkrm

    Clocks, Frames, and Data 4.3.6 Receive Clock Selection: DLB, CLKRM Table 4 shows how the digital loopback bit (DLB) and the CLKRM bit in PCR select the receiver clock. In digital loopback mode (DLB = 1), the transmitter clock drives the receiver. CLKRM determines whether the CLKR pin is an input or an output.

  • Page 28: Stopping Clocks

    Clocks, Frames, and Data 4.3.8 Stopping Clocks There are two methods to stop serial clocks between data transfers. One method is using the SPI CLKSTP mode where clocks are stopped between single-element transfers. This is described in section 9. The other method is when the clocks are inputs to the McBSP (CLKXM or CLKRM = 0) and the McBSP operates in non-SPI mode.

  • Page 29: Frame Period (Fper) And Frame Width (Fwid)

    Clocks, Frames, and Data 4.4.1 Frame Period (FPER) and Frame Width (FWID) The FPER block is a 12-bit down counter that can count down the generated data clocks from 4095 to 0. FPER controls the period of active frame sync pulses.

  • Page 30: Receive Frame Sync Selection: Dlb, Fsrm, Gsync

    Clocks, Frames, and Data 4.4.2 Receive Frame Sync Selection: DLB, FSRM, GSYNC Table 6 shows how you can select various sources to provide the receive frame synchronization signal. Note that in digital loopback mode (DLB = 1), the transmit frame sync signal is used as the receive frame sync signal and that DR is internally connected to DX.

  • Page 31: Transmit Frame Sync Selection: Fsxm, Fsgm

    Clocks, Frames, and Data 4.4.3 Transmit Frame Sync Selection: FSXM, FSGM Table 7 shows how you can select the source of the transmit frame synchronization signal. The three choices are: External frame sync input The sample rate generator frame sync signal, FSG A signal that indicates a DXR-to-XSR copy has been made Table 7.

  • Page 32: Data And Frames

    Clocks, Frames, and Data Data and Frames 4.5.1 Frame Synchronization Phases Frame synchronization indicates the beginning of a transfer on the McBSP. The data stream following frame synchronization can have up to two phases, phase 1 and phase 2. The number of phases can be selected by the phase bit, (R/X)PHASE, in RCR and XCR.

  • Page 33: Frame Length: Rfrlen1/2, Xfrlen1/2

    Clocks, Frames, and Data Table 8. RCR/XCR Fields Controlling Elements per Frame and Bits per Element RCR/XCR Field Control Serial Port Serial Port Elements per Frame Bits per Element McBSP0/1 Frame Phase Receive RFRLEN1 RWDLEN1 Receive RFRLEN2 RWDLEN2 Transmit XFRLEN1 XWDLEN1 Transmit XFRLEN2...

  • Page 34: Element Length: Rwdlen1/2, Xwdlen1/2

    Clocks, Frames, and Data 4.5.3 Element Length: RWDLEN1/2, XWDLEN1/2 The (R/X)WDLEN1/2 fields in the receive/transmit control register (RCR and XCR) determine the element length in bits per element for the receiver and the transmitter for each phase of the frame, as indicated in Table 8. Table 10 shows how the value of these fields selects particular element lengths in bits.

  • Page 35: Single-Phase Frame Of Four 8-Bit Elements

    Clocks, Frames, and Data Figure 11. Single-Phase Frame of Four 8-Bit Elements Element 1 Element 3 Element 2 Element 4 CLKR Á Á RBR-to-DRR copy RBR-to-DRR copy RBR-to-DRR copy RBR-to-DRR copy CLKX Á Á Á Á Á Á Á Á Á...

  • Page 36: Data Delay: Rdatdly, Xdatdly

    Clocks, Frames, and Data 4.5.5 Data Delay: RDATDLY, XDATDLY The start of a frame is defined by the first clock cycle in which frame synchronization is active. The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required. This delay is called data delay.

  • Page 37: Receive Data Justification And Sign Extension: Rjust

    Clocks, Frames, and Data Another common operation uses a data delay of 2. This configuration allows the serial port to interface to different types of T1 framing devices in which the data stream is preceded by a framing bit. During the reception of such a stream with a data delay of two bits, the framing bit appears after a 1-bit delay and data appears after a 2-bit delay).

  • Page 38: 32-Bit Bit Reversal: Rwdrevrs, Xwdrevrs

    Clocks, Frames, and Data 4.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS The 32-bit bit reversal feature is only available on the C621x/C671x/C64x DSP. Normally all transfers are sent and received with the MSB first. However, you can reverse the receive/transmit bit ordering of a 32-bit element (LSB first) by setting all of the following: (R/X)WDREVRS = 1 in the receive/transmit control register (RCR/XCR).

  • Page 39: Ac97 Bit Timing Near Frame Synchronization

    Clocks, Frames, and Data Figure 15 shows the AC97 timing near frame synchronization. First the frame sync pulse itself overlaps the first element. In McBSP operation, the inactive-to-active transition of the frame synchronization signal actually indicates frame synchronization. For this reason, frame synchronization can be high for an arbitrary number of bit clocks.

  • Page 40: Double-Rate St-Bus Clock

    Clocks, Frames, and Data 4.6.2 Double-Rate ST-BUS Clock Figure 17 shows the McBSP timing to be compatible with the Mitel ST-BUS. The operation is running at maximum frame frequency. CLK(R/X)M = 1: CLK(R/X)_int generated internally by the sample rate generator GSYNC = 1: CLKG is synchronized with the external frame sync signal input on FSR.

  • Page 41: Single-Rate St-Bus Clock

    Clocks, Frames, and Data 4.6.3 Single-Rate ST-BUS Clock The example in Figure 18 is the same as the ST-BUS example, except for the following items: CLKGDV = 0: CLKS drives CLK(R/X)_int without any divide down (single-rate clock). CLKSP = 0: The rising edge of CLKS generates internal clocks CLKG and CLK(R/X)_int.

  • Page 42: Double-Rate Clock

    Clocks, Frames, and Data 4.6.4 Double-Rate Clock The example in Figure 19 is the same as the ST-BUS example, except for the following: CLKSP = 0: The rising edge of CLKS generates CLKG and CLK(R/X). CLKGDV = 1: CLKG, CLKR_int, and CLKX_int frequencies are half of the CLKS frequency.

  • Page 43: Mcbsp Standard Operation

    McBSP Standard Operation McBSP Standard Operation During a serial transfer, there are typically periods of serial port inactivity between packets or transfers. The receive and transmit frame synchronization pulse occurs for every serial transfer. When the McBSP is not in the reset state and has been configured for the desired operation, a serial transfer can be initiated by programming (R/X)PHASE = 0 for a single-phase frame with the required number of elements programmed in (R/X)FRLEN1.

  • Page 44: Receive Operation

    McBSP Standard Operation Receive Operation Figure 21 shows serial reception. Once the receive frame synchronization signal (FSR) transitions to its active state, it is detected on the first falling edge of the receiver’s CLKR. The data on the DR pin is then shifted into the receive shift register (RSR) after the appropriate data delay as set by RDATDLY.

  • Page 45: Transmit Operation

    McBSP Standard Operation Transmit Operation Once transmit frame synchronization occurs, the value in the transmit shift register (XSR) is shifted out and driven on the DX pin after the appropriate data delay as set by XDATDLY. XRDY is activated after every DXR-to-XSR copy on the following falling edge of CLKX, indicating that the data transmit register (DXR) can be written with the next data to be transmitted.

  • Page 46: Maximum Frame Frequency

    McBSP Standard Operation Maximum Frame Frequency The frame frequency is determined by the following equation, which calculates the period between frame synchronization signals: clock frequency Frame frequency + Number of bit clocks between frame sync signals The frame frequency may be increased by decreasing the time between frame synchronization signals in bit clocks (which is limited only by the number of bits per frame).

  • Page 47: Frame Synchronization Ignore

    McBSP Standard Operation Frame Synchronization Ignore The McBSP can be configured to ignore transmit and receive frame synchronization pulses. The (R/X)FIG bit in (R/X)CR can be cleared to 0 to recognize frame sync pulses, or it can be set to 1 to ignore frame sync pulses. In this way, you can use (R/X)FIG either to pack data, if operating at maximum frame frequency, or to ignore unexpected frame sync pulses.

  • Page 48: Unexpected Frame Synchronization With (R/X)Fig = 0

    McBSP Standard Operation Figure 24. Unexpected Frame Synchronization With (R/X)FIG = 0 CLK(R/X) Frame sync aborts current transfer FS(R/X) New data received Current data retransmitted (R/X)SYNCERR Figure 25 shows McBSP operation when unexpected internal or external frame synchronization signals are ignored by setting (R/X)FIG = 1. Here, the transfer of element B is not affected by an unexpected frame synchronization.

  • Page 49: Data Packing Using Frame Sync Ignore Bits

    McBSP Standard Operation 5.4.2 Data Packing using Frame Sync Ignore Bits Section 4.5.4 describes one method of changing the element length and frame length to simulate 32-bit serial element transfers, thus requiring much less bus bandwidth than four 8-bit transfers require. This example works when there are multiple elements per frame.

  • Page 50: Serial Port Exception Conditions

    McBSP Standard Operation Figure 27. Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 Element 1 CLKR Frame ignored Frame ignored Frame ignored RBR-to-DRR copy CLKX Frame ignored Frame ignored Frame ignored DXR-to-XSR copy Serial Port Exception Conditions There are five serial port events that can constitute a system error: Receive overrun (RFULL = 1) Unexpected receive frame synchronization (RSYNCERR = 1) Transmit data overwrite...

  • Page 51: Serial Port Receive Overrun

    McBSP Standard Operation The data arriving on DR is continuously shifted into RSR. Once a complete element is shifted into RSR, an RSR-to-RBR transfer can occur only if an RBR-to-DRR copy is complete. Therefore, if DRR has not been read by the CPU or the DMA controller since the last RBR-to-DRR transfer (RRDY = 1), an RBR-to-DRR copy does not take place until RRDY = 0.

  • Page 52: Unexpected Receive Frame Synchronization: Rsyncerr

    McBSP Standard Operation Figure 29 shows the case in which RFULL is set but the overrun condition is averted by reading the contents of DRR at least two and a half cycles before the next element, C, is completely shifted into RSR. This ensures that a RBR-to-DRR copy of data B occurs before the next element is transferred from RSR to RBR.

  • Page 53: Decision Tree Response To Receive Frame Synchronization Pulse

    McBSP Standard Operation Case 3: Unexpected receive frame synchronization with RFIG = 0 (unexpected frame not ignored). This case was shown in Figure 24 for maximum packet frequency. Figure 31 shows this case during normal operation of the serial port with time intervals between packets. Unexpected frame sync pulses are detected when they occur the value in RDATDLY bit clocks before the last bit of the previous element is received on DR.

  • Page 54: Transmit With Data Overwrite

    McBSP Standard Operation Figure 31. Unexpected Receive Synchronization Pulse Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CLKR Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Unexpected frame synchronization Á...

  • Page 55: Transmit Empty: Xempty

    McBSP Standard Operation 5.5.4 Transmit Empty: XEMPTY XEMPTY indicates whether the transmitter has experienced under flow. Either of the following conditions causes XEMPTY to become active (XEMPTY = 0): During transmission, DXR has not been loaded since the last DXR-to-XSR copy, and all bits of the data element in XSR have been shifted out on DX.

  • Page 56: Unexpected Transmit Frame Synchronization: Xsyncerr

    McBSP Standard Operation Figure 34. Transmit Empty Avoided CLKX Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á XRDY Write of DXR (C) DXR-to-XSR copy (B)
  • Page 57 McBSP Standard Operation Case 2: FSX pulses with normal serial port transmission. This situation is discussed in section 5.3. There are two possible reasons for a transmit not to be in progress: This FSX pulse is the first one to occur after XRST = 1. The serial port is in the interpacket intervals.

  • Page 58: Decision Tree Response To Transmit Frame Synchronization Pulse

    McBSP Standard Operation Figure 35. Decision Tree Response to Transmit Frame Synchronization Pulse Transmit frame sync pulse occurs. Case 2: Unexpected Normal transmission frame sync pulse ? Start new transmit. Case 3: Abort transfer. XFIG = 1 ? Set XSYNCERR. Restart current transfer.

  • Page 59: M-Law/A-Law Companding Hardware Operation

    µ-LAW/A-LAW Companding Hardware Operation m-Law/A-Law Companding Hardware Operation m-Law/A-Law Companding Hardware Operation Companding (compressing and expanding) hardware allows compression and expansion of data in either µ-law or A-law format. The specification for µ-law and A-law log PCM is part of the CCITT G.711 recommendation. The companding standard employed in the United States and Japan is µ-law and allows 14 bits of dynamic range.

  • Page 60: Companding Internal Data

    µ-LAW/A-LAW Companding Hardware Operation m-Law/A-Law Companding Hardware Operation Figure 38. Companding Data Formats LAW16 µ-Law Value LAW16 A-law Value Figure 39. Transmit Data Companding Format in DXR DXR bits Don’t care LAW16 Table 12. Justification of Expanded Data in DRR DRR Bits RJUST LAW16...

  • Page 61: Bit Ordering

    µ-LAW/A-LAW Companding Hardware Operation m-Law/A-Law Companding Hardware Operation Figure 40 shows two methods by which the McBSP can compand internal data. Data paths for these two methods are indicated by (DLB) and (non-DLB) arrows. Non-DLB: When both the transmit and receive sections of the serial port are reset, DRR and DXR are internally connected through the companding logic.

  • Page 62: Mcbsp Initialization Procedure

    McBSP Initialization Procedure McBSP Initialization Procedure The McBSP initialization procedure varies depending on the specific system setup. Section 7.1 provides a general initialization sequence. Section 7.2 provides an initialization sequence for the special case when the external device provides the transmit frame sync FSX (FSXM = 0). The transmitter and the receiver of the McBSP can operate independently from each other.

  • Page 63: General Initialization Procedure

    McBSP Initialization Procedure Table 14. Transmitter Clock and Frame Configurations CLKX source FSX source Comment on Configuration Internal Internal The McBSP internal sample rate generator is used by the transmitter. The transmitter can generate frame sync FSX in one of two ways. First, it can generate FSX by using the internal frame sync generator (FSGM = 1).
  • Page 64 McBSP Initialization Procedure 4) Skip this step if the bit clock is provided by the external device. This step only applies if the McBSP is the bit clock master and the internal sample rate generator is used. a) Start the sample rate generator by setting the GRST bit to 1. Wait two CLKG bit clocks for synchronization.

  • Page 65: Special Case: External Device Is The Transmit Frame Master

    McBSP Initialization Procedure 8) If the internal frame sync generator is used (FSGM = 1), proceed to the additional steps to turn on the internal frame sync generator. Initialization is complete if any one of the following is true: a) The external device generates frame sync FSX and/or FSR. The McBSP is now ready to transmit and/or receive upon receiving external frame sync.
  • Page 66 McBSP Initialization Procedure The interrupt service routine must first be setup according to the description in step 9. Then follow this modified procedure for proper initialization: 1) Ensure that no portion of the McBSP is using the internal sample rate generator signal CLKG and the internal frame sync generator signal FSG (GRST = FRST = 0).
  • Page 67 McBSP Initialization Procedure 7) Setup data acquisition as required: a) If the DMA/EDMA is used to service the McBSP, setup data acquisition as desired and start the DMA/EDMA in this step, before the McBSP is taken out of reset. b) If CPU interrupt is used to service the McBSP, no action is required in this step.

  • Page 68: Multichannel Selection Operation

    Multichannel Selection Operation Multichannel Selection Operation The multichannel selection mode allows the McBSP to select independent channels (elements) for transmit and receive in a single-phase frame. Each frame represents a time-division multiplexed data stream. For all of the McBSP, up to 32 elements in a bit stream of up to 128 elements can be enabled at any given time.

  • Page 69: Enabling Multichannel Selection

    Multichannel Selection Operation Enabling Multichannel Selection Multichannel mode can be enabled independently for reception and transmission by setting the RMCM bit to 1 and the XMCM bit to a nonzero value in MCR, respectively. Enabling and Masking of Channels in Normal Multichannel Selection Mode This section describes how to enable the channels in normal multichannel selection mode.
  • Page 70 Multichannel Selection Operation Transmit data masking allows an element enabled for transmit to have its DX pin set to the high-impedance state during its transmit period. In systems where symmetric transmit and receive provides software benefits, this feature allows transmit elements to be disabled on a shared serial bus. A similar feature is not needed for receive, because multiple receptions cannot cause serial bus contention.

  • Page 71: Xmcm Operation

    Multichannel Selection Operation high-impedance state. For receiving, a RBR-to-DRR copy occurs only for those elements that are selected via RP(A/BBLK and RCER. If RINT were to be generated for every RBR-to-DRR copy, it would occur as many times as the number of elements selected in RCER (and not the number of elements programmed in RFRLEN1).
  • Page 72 Multichannel Selection Operation Figure 42. XMCM Operation (Continued) (b) XMCM = 01b, XPABLK = 00b, XCER = 1010b XRDY DXR-to-XSR copy (E3) Write of DXR (E3) DXR-to-XSR (E1) (c) XMCM = 10b, XPABLK = 00b, XCER = 1010b XRDY DXR-to-XSR copy (E3) DXR-to-XSR copy Write of DXR...

  • Page 73: Changing Element Selection

    Multichannel Selection Operation 8.2.1 Changing Element Selection Using the multichannel selection feature, a static group of 32 elements can be enabled and remains enabled with no CPU intervention until this allocation is modified. An arbitrary number of, group of, or all of the elements within a frame can be accessed by updating the block allocation registers during the course of the frame in response to the end-of-subframe interrupts (see section 8.2.2 for information about these interrupts).
  • Page 74 Multichannel Selection Operation When the RMCME and XMCME bits are cleared to 0, the C64x McBSP is in the normal multichannel selection mode. See section 8.2 for a detailed description. In normal multichannel selection mode, RCERE1−RCERE3 and XCERE1−XCERE3 are not used; RCERE0 and XCERE0 function as RCER and XCER, respectively.

  • Page 75: Dx Enabler: Dxena

    Multichannel Selection Operation XMCM = 11b: In this mode, symmetric transmit and receive operation is forced. Select desired receive channels setting RCERE0−RCERE3. The elements enabled in XCERE0−XCERE3 can be either a subset of or the same as those selected in RCERE0−RCERE3. In this mode all elements are disabled, so DR and DX are in the high-impedance state.
  • Page 76 Multichannel Selection Operation In the case when two McBSPs are used to transmit data over the same TDM line, bus contention occurs if DXENA = 0. The first McBSP turns off the transmission of the last data bit (changes DX from valid to a high-impedance state) after a disable time specified in the datasheet.

  • Page 77: Spi Protocol: Clkstp

    SPI Protocol: CLKSTP SPI Protocol: CLKSTP A system conforming to the SPI protocol has a master-slave configuration. The SPI protocol is a 4-wire interface composed of serial data in (master in slave out or MISO), serial data out (master out slave in or MOSI), shift clock (SCK), and an active (low) slave enable (SS) signal.

  • Page 78: Spi Transfer With Clkstp = 10B

    SPI Protocol: CLKSTP The clock stop mode (CLKSTP) of the McBSP provides compatibility with the SPI protocol. The McBSP supports two SPI transfer formats that are specified by the clock stop mode bits (CLKSTP) in SPCR. The CLKSTP bits in conjunction with the CLKXP bit in PCR allows serial clocks to be stopped between transfers using one of four possible timing variations, as shown in Table 15.

  • Page 79: Spi Transfer With Clkstp = 11B

    SPI Protocol: CLKSTP Figure 47. SPI Transfer with CLKSTP = 11b Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CLKX (CLKXP=0)/SCK Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CLKX (CLKXP=1)/SCK Á...

  • Page 80: Mcbsp Operation As The Spi Master

    SPI Protocol: CLKSTP When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or a slave. The McBSP is a master when it generates clocks. When the McBSP is the SPI master, CLKX drives both its own internal receive clock (CLKR) and the serial clock (SCK) of the SPI slave.

  • Page 81: Mcbsp Operation As The Spi Slave

    SPI Protocol: CLKSTP McBSP Operation as the SPI Slave When the McBSP is an SPI slave device, the master clock CLKX and slave enable FSX are generated by an external SPI master, as shown in Figure 45. Thus, the CLKX and FSX pins are configured as inputs by clearing the CLKXM and FSXM bits in PCR to 0.
  • Page 82 SPI Protocol: CLKSTP 4) Wait two bit clocks for the McBSP to reinitialize. 5) Depending upon whether the CPU or DMA services the McBSP, perform step (a) if the CPU is used, or step (b) if the DMA is used. a) If the CPU is used to service the McBSP.

  • Page 83: Mcbsp Pins As General-Purpose I/O

    McBSP Pins as General-Purpose I/O McBSP Pins as General-Purpose I/O Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR, DR, and CLKS) to be used as general-purpose I/O pins rather than serial port pins: The related portion (transmitter or receiver) of the serial port is in reset: (R/X)RST = 0 in SPCR General-purpose I/O is enabled for the related portion of the serial port: (R/X)IOEN = 1 in PCR...

  • Page 84: Mcbsp Registers For C620X/C670X Dsp

    Registers Registers Table 17 lists the McBSP registers and their memory addresses for the C620x/C670x DSP, Table 18 lists McBSP registers C621x/C671x DSP, and Table 19 lists the McBSP registers for the C64x DSP. See the device-specific datasheet for the memory address of these registers. The McBSP control registers are accessible only via the peripheral bus (see Figure 1).

  • Page 85: Mcbsp Registers For C621X/C671X Dsp

    Registers Table 18. McBSP Registers for C621x/C671x DSP McBSPs on Device Acronym Register Name McBSP 0 McBSP 1 Section † Receive buffer register RBR0 RBR1 − † Receive shift register RSR0 RSR1 − † Transmit shift register XSR0 XSR1 − ‡§...

  • Page 86: Mcbsp Registers For C64X Dsp

    Registers Table 19. McBSP Registers for C64x DSP McBSPs on Device Acronym Register Name McBSP 0 McBSP 1 McBSP 2 ¶ Section † Receive buffer register RBR0 RBR1 RBR2 − † Receive shift register RSR0 RSR1 RSR2 − † Transmit shift register XSR0 XSR1 XSR2...

  • Page 87: Data Receive Register (Drr)

    Registers 11.1 Data Receive Register (DRR) The data receive register (DRR) contains the value to be written to the data bus. The DRR is shown in Figure 48 and described in Table 20. For devices with an EDMA, DRR is mapped to memory locations on both the EDMA bus (data port) as well as the peripheral bus (configuration bus).

  • Page 88: Data Transmit Register (Dxr)

    Registers 11.2 Data Transmit Register (DXR) The data transmit register (DXR) contains the value to be loaded into the data transmit shift register (XSR). The DXR is shown in Figure 49 and described in Table 21. For devices with an EDMA, DXR is mapped to memory locations on both the EDMA bus (data port) as well as the peripheral bus (configuration bus).

  • Page 89: Serial Port Control Register (Spcr)

    Registers 11.3 Serial Port Control Register (SPCR) The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR). The SPCR contains McBSP status control bits. The SPCR is shown in Figure 50 and described in Table 22. Figure 50.

  • Page 90: Serial Port Control Register (Spcr) Field Descriptions

    Registers Table 22. Serial Port Control Register (SPCR) Field Descriptions † † Value Description field symval 31−26 Reserved − Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. FREE For C621x/C671x and C64x DSP: Free-running enable mode bit.
  • Page 91 Registers Table 22. Serial Port Control Register (SPCR) Field Descriptions (Continued) † † Value Description field symval 21−20 XINTM 0−3h Transmit interrupt (XINT) mode bit. XRDY XINT is driven by XRDY (end-of-word) and end-of-frame in A-bis mode. XINT is generated by end-of-block or end-of-frame in multichannel operation.
  • Page 92 Registers Table 22. Serial Port Control Register (SPCR) Field Descriptions (Continued) † † Value Description field symval 14−13 RJUST 0−3h Receive sign-extension and justification mode bit. Right-justify and zero-fill MSBs in DRR. Right-justify and sign-extend MSBs in DRR. Left-justify and zero-fill LSBs in DRR. −...
  • Page 93 Registers Table 22. Serial Port Control Register (SPCR) Field Descriptions (Continued) † † Value Description field symval 5−4 RINTM 0−3h Receive interrupt (RINT) mode bit. RRDY RINT is driven by RRDY (end-of-word) and end-of-frame in A-bis mode. RINT is generated by end-of-block or end-of-frame in multichannel operation.

  • Page 94: Receive Control Register (Rcr)

    Registers 11.4 Receive Control Register (RCR) The receive control register (RCR) configures parameters of the receive operations. The RCR is shown in Figure 51 and described in Table 23 Figure 51. Receive Control Register (RCR) 24 23 21 20 RPHASE RFRLEN2 RWDLEN2 RCOMPAND...
  • Page 95 Registers Table 23. Receive Control Register (RCR) Field Descriptions (Continued) † † Value Description field symval 20−19 RCOMPAND 0−3h Receive companding mode bit. Modes other than 00 are only enabled when RWDLEN1/2 bit is 000 (indicating 8-bit data). No companding, data transfer starts with MSB first. 8BITLSB No companding, 8-bit data transfer starts with LSB first.
  • Page 96 Registers Table 23. Receive Control Register (RCR) Field Descriptions (Continued) † † Value Description field symval RWDREVRS For C621x/C671x and C64x DSP: Receive 32-bit bit reversal enable bit. 32-bit bit reversal is disabled. DISABLE 32-bit bit reversal is enabled. 32-bit data is received LSB ENABLE first.

  • Page 97: Transmit Control Register (Xcr)

    Registers 11.5 Transmit Control Register (XCR) The transmit control register (XCR) configures parameters of the transmit operations. The XCR is shown in Figure 52 and described in Table 24. Figure 52. Transmit Control Register (XCR) 24 23 21 20 XPHASE XFRLEN2 XWDLEN2 XCOMPAND...
  • Page 98 Registers Table 24. Transmit Control Register (XCR) Field Descriptions (Continued) † † Value Description field symval 20−19 XCOMPAND 0−3h Transmit companding mode bit. Modes other than 00 are only enabled when XWDLEN1/2 bit is 000 (indicating 8-bit data). No companding, data transfer starts with MSB first. 8BITLSB No companding, 8-bit data transfer starts with LSB first.

  • Page 99: Sample Rate Generator Register (Srgr)

    Registers Table 24. Transmit Control Register (XCR) Field Descriptions (Continued) † † Value Description field symval XWDREVRS For C621x/C671x and C64x DSP: Transmit 32-bit bit reversal feature enable bit. DISABLE 32-bit bit reversal is disabled. ENABLE 32-bit bit reversal is enabled. 32-bit data is transmitted LSB first.

  • Page 100: Sample Rate Generator Register (Srgr) Field Descriptions

    Registers Table 25. Sample Rate Generator Register (SRGR) Field Descriptions † † Value Description field symval GSYNC Sample-rate generator clock synchronization bit is only used when the external clock (CLKS) drives the sample-rate generator clock (CLKSM = 0). FREE The sample-rate generator clock (CLKG) is free running. SYNC The sample-rate generator clock (CLKG) is running;...

  • Page 101: Multichannel Control Register (Mcr)

    Registers 11.7 Multichannel Control Register (MCR) The multichannel control register (MCR) contains fields that control the multichannel selection mode. The enhanced 128-channel selection mode (selected by the RMCME and XMCME bits), which allows the McBSP to select 128 channels at any time, is only available on the C64x DSP (section 8.3). The MCR is shown in Figure 54 and described in Table 26.
  • Page 102 Registers Table 26. Multichannel Control Register (MCR) Field Descriptions (Continued) † † Value Description field symval 24−23 XPBBLK 0−3h Transmit partition B subframe bit. Enables 16 contiguous channels in each subframe. Subframe 1. Channel 16 to channel 31 Subframe 3. Channel 48 to channel 63 Subframe 5.
  • Page 103 Registers Table 26. Multichannel Control Register (MCR) Field Descriptions (Continued) † † Value Description field symval 17−16 XMCM 0−3h Transmit multichannel selection enable bit. ENNOMASK All channels are enabled without masking (DX is always driven during transmission of data). DX is masked or driven to a high-impedance state during (a) interpacket intervals, (b) when a channel is masked regardless of whether it is enabled, or (c) when a channel is disabled.
  • Page 104 Registers Table 26. Multichannel Control Register (MCR) Field Descriptions (Continued) † † Value Description field symval 6−5 RPABLK 0−3h Receive partition A subframe bit. Enables 16 contiguous channels in each subframe. Subframe 0. Channel 0 to channel 15 Subframe 2. Channel 32 to channel 47 Subframe 4.

  • Page 105: Receive Channel Enable Register (Rcer)

    Registers 11.8 Receive Channel Enable Register (RCER) The receive channel enable register (RCER) is used to enable any of the 32 elements for a receive. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B. The RCEA and RCEB fields in RCER enable elements within the 16-channel elements in partitions A and B, respectively.

  • Page 106: Transmit Channel Enable Register (Xcer) Field Descriptions

    Registers 11.9 Transmit Channel Enable Registers (XCER) The transmit channel enable register (XCER) is used to enable any of the 32 elements for a transmit. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B. The XCEA and XCEB fields in XCER enable elements within the 16-channel elements in partitions A and B, respectively.

  • Page 107: Enhanced Receive Channel Enable Registers (Rcere0−3)

    Registers 11.10 Enhanced Receive Channel Enable Registers (RCERE0−3) The enhanced receive channel enable registers (RCERE0, RCERE1, RCERE2, and RCERE3) are used to enable any of the 128 elements for receive. Partitions A and B do not apply to the enhanced multichannel selection mode; therefore, the bit fields in RCERE0−3 are numbered from 0 to 127, representing the 128 channels.

  • Page 108: Channel Enable Bits In Rceren For A 128-Channel Data Stream

    Registers Table 30. Channel Enable Bits in RCEREn for a 128-Channel Data Stream Channel Number of a 128-Channel Data Stream (RCEn) RCEREn 0 - 15 16 - 31 32 - 47 48 - 63 64 - 79 80 - 95 96 - 111 112-127 RCERE0...

  • Page 109: Enhanced Transmit Channel Enable Registers (Xcere0−3)

    Registers 11.11 Enhanced Transmit Channel Enable Registers (XCERE0−3) The enhanced transmit channel enable registers (XCERE0, XCERE1, XCERE2, and XCERE3) are used to enable any of the 128 elements for transmit. Partitions A and B do not apply to the enhanced multichannel selection mode; therefore, the bit fields in XCERE0−3 are numbered from 0 to 127, representing the 128 channels.

  • Page 110: Channel Enable Bits In Xceren For A 128-Channel Data Stream

    Registers Table 32. Channel Enable Bits in XCEREn for a 128-Channel Data Stream Channel Number of a 128-Channel Data Stream (XCEn) XCEREn 0 - 15 16 - 31 32 - 47 48 - 63 64 - 79 80 - 95 96 - 111 112-127 XCERE0...

  • Page 111: Pin Control Register (Pcr)

    Registers 11.12 Pin Control Register (PCR) The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR). The PCR is also used to configure the serial port pins as general-purpose inputs or outputs during receiver and/or transmitter reset (for more information see section 10).
  • Page 112 Registers Table 33. Pin Control Register (PCR) Field Descriptions (Continued) † † Value Description field symval RIOEN Receive general-purpose I/O mode only when receiver is disabled (RRST = 0 in SPCR). DR, FSR, CLKR, and CLKS pins are configured as serial port pins and do not function as general-purpose I/O pins.
  • Page 113 Registers Table 33. Pin Control Register (PCR) Field Descriptions (Continued) † † Value Description field symval CLKRM Receiver clock mode bit. Digital loop back mode is disabled (DLB = 0 in SPCR): INPUT CLKR is an input pin and is driven by an external clock. OUTPUT CLKR is an output pin and is driven by the internal sample-rate generator.
  • Page 114 Registers Table 33. Pin Control Register (PCR) Field Descriptions (Continued) † † Value Description field symval FSXP Transmit frame-synchronization polarity bit. ACTIVEHIGH Transmit frame-synchronization pulse is active high. ACTIVELOW Transmit frame-synchronization pulse is active low. FSRP Receive frame-synchronization polarity bit. ACTIVEHIGH Receive frame-synchronization pulse is active high.

  • Page 115: Document Revision History

    Revision History Table 34 lists the changes made since the previous version of this document. Table 34. Document Revision History Page Additions/Modifications/Deletions Added new sentences after third sentence in first paragraph: Non-32-bit write accesses to control registers can result in corrupting the control register value. This is because undefined values are written to non-enabled bytes.
  • Page 116 This page is intentionally left blank. Multichannel Buffered Serial Port (McBSP) SPRU580C...
  • Page 117 Index Index 32-bit bit reversal (RWDREVRS, XWDREVRS) 38 companding data format 60 companding hardware 59 companding internal data 60 configuration element length 34 bit clock polarity (CLKSP) 24 frame and clock 18, 32 bit ordering 61 frame length 33 block diagram CPU interrupts 18 clock and frame generation 19 companding of internal data 61...
  • Page 118 Index element length 34 ignore frame synchronization 47 end-of-frame interrupt 73 initialization procedure 62 enhanced multichannel selection mode input clock source mode (CLKSM) 23 (C64x DSP only) 73 interface signals 13 enhanced receive channel enable register interrupts CPU 18 (RCERE) 107 enhanced transmit channel enable register (XCERE) 109 exception conditions 50...
  • Page 119 (SPCR) 89 transmit channel enable register (XCER) 106 PCR 111 transmit control register (XCR) 97 pin control register (PCR) 111 related documentation from Texas Instruments 3 pins as general-purpose I/O 83 reset serial port 15 programmable clock 19 revision history 115...
  • Page 120 Index XCEA bits 106 XCEB bits 106 XCER 106 trademarks 4 transmission, data 15 XCERE 109 transmit channel enable register (XCER) 106 XCOMPAND bits 97 transmit control register (XCR) 97 XCR 97 transmit data companding format 60 XDATDLY bits 97 transmit empty (XEMPTY) 55 XEMPTY bit 89 transmit interrupt (XINT) 18...

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