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TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
2.3
Memory Map Summary
Table 2-2
shows the memory map address of the C6474 device. For more information about the registers
in these address ranges, click on the links in the table. The external memory configuration register
address ranges in the C6474 device begin at the hex address location 0x7000 for DDR2 Memory
Controller.
HEX ADDRESS RANGE
START
0000 0000
007F FFFF
0080 0000
0087 FFFF
0088 0000
008F FFFF
009 00000
0097 FFFF
0098 0000
009F FFFF
00A0 0000
00DF FFFF
00E0 0000
00E0 7FFF
00E0 8000
00EF FFFF
00F0 0000
00F0 7FFF
00F0 8000
00FF FFFF
0100 0000
01BF FFFF
01C0 0000
027F FFFF
0280 0000
0280 03FF
0280 0400
0287 FFFF
0288 0000
0288 00FF
0288 0100
0288 01FF
0288 0200
0288 02FF
0288 0300
0288 03FF
0288 0400
0288 0403
0288 0404
0288 0407
0288 0408
0288 040B
0288 040C
0288 07FF
0288 0800
0288 0BFF
0288 0900
0288 0903
0288 0904
0288 0907
0288 0908
0288 090B
0288 090C
0288 093F
0288 0940
0288 0943
0288 0944
0288 0947
0288 0948
0288 094B
0288 0C00
028B FFFF
028C 0000
028C 00FF
028C 0100
028C FFFF
028D 0000
208D 00FF
028D 0100
028D FFFF
028E 0000
028F FFFF
0290 0000
0290 003F
0290 0040
0290 FFFF
0291 0000
0291 003F
0291 0040
0291 FFFF
0292 0000
0292 003F
0292 0040
0292 FFFF
0293 0000
0293 003F
0293 0040
0293 FFFF
0294 0000
0294 003F
0294 0040
0294 FFFF
12
Device Overview
Table 2-2. Memory Map Summary
SIZE
END
8M
512K
512K
512K
512K
4M
32K
1M - 32K
32K
1M - 32K
4M
12.5M
Control Registers on CFG SCR
1K
511K
256
256
256
256
4
4
4
1K- 6
1K
4B
4B
4B
52B
4B
4B
4B
253K
256
64K - 256
256
64K - 256
128K
64
64K - 64
64
64K - 64
64
64K - 64
64
64K - 64
64
64K - 64
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Product Folder Link(s)
MEMORY BLOCK DESCRIPTION
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
Internal RAM
C64x+ Megamodule Registers
Frame Synchronization (FSYNC)
Chip Interrupt Controller 0 (CIC0)
Chip Interrupt Controller 1 (CIC1)
Chip Interrupt Controller 2 (CIC2)
Chip Interrupt Controller 3 (CIC3)
DSP Trace Formatter 1 (DTF1)
DSP Trace Formatter 2 (DTF2)
DSP Trace Formatter 3 (DTF3)
Timer Pin Manager (TPMGR)
Copyright © 2008–2010, Texas Instruments Incorporated
:TMS320C6474
Reserved
L2 SRAM
Reserved
Reserved
Reserved
L1P SRAM
Reserved
L1D SRAM
Reserved
Reserved
Reserved
Reserved
CFGC
IPCGR0
IPCGR1
IPCGR2
Reserved
IPCAR0
IPCAR1
IPCAR2
Reserved
McBSP0
Reserved
McBSP1
Reserved
Reserved
Reserved
Timer0
Reserved
Timer1
Reserved
Timer2
Reserved
Timer3
Reserved
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