Loads In Pipeline From Example - Texas Instruments TMS320C6000 Series Reference Manual

Table 5–4. Loads in Pipeline From Example 5–2
Figure 5–24. 4-Bank Interleaved Memory With Two Memory Spaces
i
LDW .D1 E1
Bank 0
LDW .D2 E1
Bank 0
† Stall due to memory bank hit
For devices that have more than one memory space (see Figure 5–24), an
access to bank 0 in one space does not interfere with an access to bank 0 in
another memory space, and no pipeline stall occurs.
Memory
0 1
space 0
8 9
8N 8N + 1
Bank 0
8M 8M + 1
Memory
space 1
Bank 0
The internal memory of the 'C62x family varies from device to device. See the
TMS320C6201/C6701 Peripherals Reference Guide to determine the
memory spaces in your particular device.
i + 1 i + 2
E2 E3
E2
2 3
10 11
8N + 2 8N + 3 8N + 4
Bank 1
8M + 2 8M + 3 8M + 4
Bank 1
TMS320C62x Pipeline
Performance Considerations
i + 3 i + 4
E4
E3 E4
4 5 6
12 13 14
8N + 5 8N + 6 8N + 7
Bank 2 Bank 3
8M + 5 8M + 6 8M + 7
Bank 2 Bank 3
i + 5
E5
E5
7
15
5-25