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TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP
Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP Manuals
Manuals and User Guides for Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP. We have
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Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP manual available for free PDF download: User Manual
Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP User Manual (79 pages)
DSP Turbo-Decoder Coprocessor 2 (TCP2)
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
8
Read this First
8
Features
9
Introduction
10
3GPP and IS2000 Turbo-Encoder Block Diagram
10
Overview
11
3GPP and IS2000 Turbo-Decoder Block Diagram
11
Standalone (SA) Mode
12
TCP2 Block Diagram
12
Frame Sizes for Standalone (SA) Mode and Shared-Processing (SP) Mode
12
Input Data Format
13
Standalone (SA) Mode Block Diagram
13
Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and
14
EN = 1 (Little-Endian Mode) Rate
14
EN = 0 (Big-Endian Mode) Rate
14
EN = 0 (Big-Endian Mode) Rate
15
EN = 1 (Little-Endian Mode) Rate
15
Output Decision Data Format
16
Stopping Criteria
16
Rate 3/4 en = 0 (Big-Endian Mode) Rate
16
Interleaver Data
16
Stopping Test Unit
17
Shared-Processing (SP) Mode
18
Shared-Processing (SP) Mode Block Diagram
19
Subframe Equations
20
Frame Process
20
Input Data Format
22
TCP2 Shared Processing Block Diagram
22
Systematic/Parity Data for Rates 1/2, 1/3, 1/4, 1/5, and
22
EN = 1 (Little-Endian Mode) Rate
22
EN = 0 (Big-Endian Mode) Rate
22
EN = 1 (Little-Endian Mode) Rate
23
EN = 0 (Big-Endian Mode) Rate
23
Output Data Format
24
EN = 0 (Big-Endian Mode) Rate
24
EN = 1 (Little-Endian Mode) Rate
24
Rate 3/4 en = 0 (Big-Endian Mode) Rate
24
A Priori Data
24
Registers
25
TCP2 Rams
25
Peripheral Identification Register (PID)
27
TCP2 Registers
25
Peripheral Identification Register (PID) Field Descriptions
27
TCP2 Input Configuration Register 0 (TCPIC0)
28
TCP2 Input Configuration Register 0 (TCPIC0) Field Descriptions
28
TCP2 Input Configuration Register 1 (TCPIC1)
29
TCP2 Input Configuration Register 2 (TCPIC2)
29
TCP2 Input Configuration Register 1 (TCPIC1) Field Desccriptions
29
TCP2 Input Configuration Register 2 (TCPIC2) Field Descriptions
29
TCP2 Input Configuration Register 3 (TCPIC3)
30
TCP2 Input Configuration Register 4 (TCPIC4)
31
TCP2 Input Configuration Register 4 (TCPIC4) Field Descriptions
31
TCP2 Input Configuration Register 5 (TCPIC5)
32
Tail Symbols
32
CRC Examples
32
TCP2 Input Configuration Register 6 (TCPIC6)
33
TCP2 Input Configuration Register 5 (TCPIC5) Field Descriptions
32
TCP2 Input Configuration Register 6 (TCPIC6) Field Descriptions
33
TCP2 Input Configuration Register 7 (TCPIC7)
34
TCP2 Input Configuration Register 7 (TCPIC7) Field Descriptions
34
TCP2 Input Configuration Register 8 (TCPIC8)
35
TCP2 Input Configuration Register 8 (TCPIC8) Field Descriptions
35
TCP2 Input Configuration Register 9 (TCPIC9)
36
CP2 Input Configuration Register 9 (TCPIC9)
36
CP2 Input Configuration Register 9 (TCPIC9) Field Descriptions
36
TCP2 Input Configuration Register 10 (TCPIC10)
37
TCP2 Input Configuration Register 11 (TCPIC11)
37
TCP2 Input Configuration Register 10 (TCPIC10) Field Descriptions
37
TCP2 Input Configuration Register 11 (TCPIC11)
38
TCP2 Input Configuration Register 11 (TCPIC11) Field Descriptions
38
TCP2 Input Configuration Register 12 (TCPIC12)
39
TCP2 Input Configuration Register 13 (TCPIC13)
39
TCP2 Input Configuration Register 12 (TCPIC12) Field Descriptions
39
TCP2 Input Configuration Register 13 (TCPIC13) Field Descriptions
39
TCP2 Input Configuration Register 14 (TCPIC14)
40
TCP2 Input Configuration Register 14 (TCPIC14) Field Descriptions
40
TCP2 Input Configuration Register 15 (TCPIC15)
41
Extrinsic Scale Registers
41
TCP2 Output Parameter Register 0 (TCPOUT0)
42
TCP2 Output Parameter Register 1 (TCPOUT1)
42
TCP2 Input Configuration Register 15 (TCPIC15) Field Descriptions
41
TCP2 Output Parameter Register 0 (TCPOUT0) Field Descriptions
42
TCP2 Output Parameter Register 1 (TCPOUT1) Field Descriptions
42
TCP2 Output Parameter Register 2 (TCPOUT2)
43
TCP2 Execution Register (TCPEXE)
43
TCP2 Execution Register (TCPEXE) Field Descriptions
43
TCP2 Endian Register (TCPEND)
44
TCP2 Output Parameter Register 2 (TCPOUT2) Field Descriptions
43
TCP2 Endian Register (TCPEND) Field Descriptions
44
TCP2 Error Register (TCPERR)
45
TCP2 Error Register (TCPERR) Field Descriptions
45
TCP2 Status Register (TCPSTAT)
47
TCP2 Status Register (TCPSTAT) Field Descriptions
47
TCP2 Emulation Register (TCPEMU)
49
TCP2 Emulation Register (TCPEMU) Field Descriptions
49
Data Destination - EDMA3 (Big Endian)
50
Data Destination - Kernel (Little Endian)
50
Data Source - EDMA3 (Big Endian)
50
Data Source - Kernel (Little Endian)
50
Endianness
50
Data Memory for Systematic
50
Data Memory
51
EN = 0 (Big-Endian Mode) Rate = 1/2
51
EN = 0 (Big-Endian Mode) Rate = 1/3
51
EN = 1 (Little-Endian Mode) Rate = 1/2
51
EN = 1 (Little-Endian Mode) Rate = 1/3
51
EN = 1 (Little-Endian Mode) Rate = 1/4
51
EN = 0 (Big-Endian Mode) Rate = 1/4
52
EN = 0 (Big-Endian Mode) Rate = 1/5
52
EN = 1 (Little-Endian Mode) Rate = 3/4
52
EN = 0 (Big-Endian Mode) Rate = 3/4
53
EN = 1 (Little-Endian Mode) Rate = 1/5
52
Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0)
53
Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0)
53
Source of Endianness Manager - Trellis Stage Ordering of Hard Decisions in 32-Bit Word
53
Destination of Endianness Manager (OUT_ORDER = 0)
54
Data Destination = EDMA3 en = 0 (Big-Endian Mode)
54
Data Source = Kernel
54
Hard Decisions in DSP Memory
54
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1)
54
Interleaver Data
55
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)
55
TCP_ENDIAN Programming Register
55
TCP_ENDIAN Register
55
Data Destination - Kernel (ENDIAN_INTR = 1)
56
Data Source - EDMA3 (ENDIAN_INTR = 1)
56
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 0)
56
Interleaver Indexes in DSP Memory (ENDIAN_INTR = 1)
56
Data Destination - Kernel (ENDIAN_INTR = 0)
57
Data Source - EDMA3 (ENDIAN_INTR = 0)
57
Extrinsic Data
57
Extrinsic in DSP Memory (ENDIAN_EXTR = 1)
57
Data Destination - EDMA3 (ENDIAN_EXTR = 1)
58
Data Source - Kernel (ENDIAN_EXTR = 1)
58
Architecture
59
Data Destination - EDMA3 (ENDIAN_EXTR = 0)
59
Sub-Block and Sliding Window Segmentation
60
Data Source - Kernel (ENDIAN_EXTR = 0)
59
Extrinsic in DSP Memory (ENDIAN_EXTR = 0)
59
MAP Unit Block Diagram
60
Subframe Segmentation (SP Mode Only)
61
Sliding Windows and Sub-Blocks Segmentation (Example with 5 Sub-Blocks, Frame Length 20730)
61
Examples for NUM_BLOCK, NUM_SUBBLOCK, NUM_SW, and WIN_REL
61
Reliability and Prolog Length Calculation
62
Shared Processing Subframe Segmentation (Example with 5 Subframes)
62
Added Features
63
Example R Formula
63
Programming
64
Valid Re-Encode Symbols Used for Comparison
64
EDMA3 Resources
65
EDMA3 Parameters in Shared Processing (SP) Mode
65
Programming Standalone (SA) Mode
66
Programming Shared-Processing (SP) Mode
70
EDMA3 Parameters in Standalone (SA) Mode
65
EDMA3 Parameters Structure
65
Input Configuration Parameters Settings in Standalone (SA) Mode
70
Output Parameters
74
Events Generation
74
TCP2 Events Generation in Standalone (SA) Mode
74
Input Configuration Parameters Settings in Shared-Processing (SP) Mode
74
Debug Mode: Pause after each Map
75
Errors and Status
75
13.1 Errors
75
TCP2 Events Generation in Shared-Processing (SP) Mode
75
13.2 Status
77
Important Notice
79
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