Texas Instruments TMS320C6670 Data Manual
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Texas Instruments TMS320C6670 Data Manual

Texas Instruments TMS320C6670 Data Manual

Multicore fixed and floating-point system-on-chip
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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS689D
March 2012

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Summary of Contents for Texas Instruments TMS320C6670

  • Page 1 TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS689D...
  • Page 2 Added a note on Level Interrupts and EOI values for various modules Corrected the address range for I C MMRs and corrected extended temp max to 100C from 105C SPRS689 February 2011 Initial Release For detailed revision information, see ‘‘Revision History’’ on page A-219. Release History Copyright 2012 Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    5.1.3 L2 Memory ..................... . . 101 Copyright 2012 Texas Instruments Incorporated...
  • Page 4 7 TMS320C6670 Peripheral Information and Electrical Specifications ........
  • Page 5 B.2 Packaging Information ....................221 Copyright 2012 Texas Instruments Incorporated...
  • Page 6 C66x™ DSP Device Nomenclature (including the TMS320C6670 DSP)........
  • Page 7 AIF2 Timer External Frame Event Timing ............... . .215 Copyright 2012 Texas Instruments Incorporated...
  • Page 8 JTAG Test-Port Timing ...................218 List of Figures Copyright 2012 Texas Instruments Incorporated...
  • Page 9 Clock Sequencing ....................115 Copyright 2012 Texas Instruments Incorporated...
  • Page 10 Configuration Register Field Descriptions ............... .188 List of Tables Copyright 2012 Texas Instruments Incorporated...
  • Page 11 Thermal Resistance Characteristics (PBGA Package) [CYP] ............221 Copyright 2012 Texas Instruments Incorporated...
  • Page 12 TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip SPRS689D—March 2012 www.ti.com List of Tables Copyright 2012 Texas Instruments Incorporated...

  • Page 13: Tms320C6670 Features

    – - 40°C to 100°C Copyright 2012 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

  • Page 14: Keystone Architecture

    1.2 Device Description The TMS320C6670 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure applications. The C6670 provides a very high performance macro basestation platform for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.
  • Page 15 The C6670 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. Copyright 2012 Texas Instruments Incorporated TMS320C6670 Features...

  • Page 16: Functional Block Diagram

    TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip SPRS689D—March 2012 www.ti.com 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the TMS320C6670 device. Figure 1-1 Functional Block Diagram Coprocessors Memory Subsystem ´ 64-Bit DDR3 EMIF SRAM MSMC RSA RSA Debug &...

  • Page 17: Device Overview

    2.1 Device Characteristics Table 2-1 provides an overview of the TMS320C6670 SoC. The table shows the significant features of the device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1...
  • Page 18 1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
  • Page 19 For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following documents (2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66): • C66x CPU and Instruction Set Reference Guide •...

  • Page 20: Figure 2-1 Cpu (Dsp Core) Data Paths

    ´ ´ Register src2 File B (B0, B1, B2, ...B31) src1 dst1 dst2 src2_hi src2 src1_hi src1 Data Path B src2 src1 src2 src1 Control Register 66xx Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 21: Memory Map Summary

    Multicore Fixed and Floating-Point System-on-Chip SPRS689D—March 2012 www.ti.com 2.2 Memory Map Summary Table 2-2 shows the memory map address ranges of the TMS320C6670 device. Table 2-2 Memory Map Summary (Part 1 of 9) Logical 32 bit Address Physical 36 bit Address...

  • Page 22: Table 2-6 Table

    0 021F 0000 0 021F 07FF FFTC-A configuration 021F 0800 021F 3FFF 0 021F 0800 0 021F 3FFF Reserved 021F 4000 021F 47FF 0 021F 4000 0 021F 47FF FFTC-B configuration Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 23: Table

    0 0234 FFFF Reserved 0235 0000 0235 0FFF 0 0235 0000 0 0235 0FFF Power Sleep Controller (PSC) 0235 1000 0235 FFFF 0 0235 1000 0 0235 FFFF 64K-4K Reserved Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 24 0 0254 0000 0 0254 003F UART 0254 0400 0254 FFFF 0 0254 0400 0 0254 FFFF 64K-64 Reserved 0255 0000 0257 FFFF 0 0255 0000 0 0257 FFFF 192K Reserved Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 25 0 027A 0400 0 027A 7FFF Reserved 027A 8000 027A 83FF 0 027A 8000 0 027A 83FF EDMA3CC2 transfer controller EDMA3TC3 027A 8400 027A FFFF 0 027A 8400 0 027A FFFF Reserved Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 26 0 10F0 8000 0 117F FFFF 9M-32K Reserved 1180 0000 118F FFFF 0 1180 0000 0 118F FFFF CorePac1 L2 SRAM 1190 0000 11DF FFFF 0 1190 0000 0 11DF FFFF Reserved Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 27 0 17E0 0000 0 17E0 7FFF Reserved 17E0 8000 17EF FFFF 0 17E0 8000 0 17EF FFFF 1M-32K Reserved 17F0 0000 17F0 7FFF 0 17F0 0000 0 17F0 7FFF Reserved Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 28 0 341F FFFF Queue Manager subsystem data 3420 0000 342F FFFF 0 3420 0000 0 342F FFFF Reserved 3430 0000 3439 FFFF 0 3430 0000 0 3439 FFFF 640K Reserved Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 29: Boot Sequence

    BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be completed. For more details on boot sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 66. Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 30: Boot Modes Supported And Pll Settings

    2 = Ethernet (SGMII) (PA driven from core clk) 3 = Ethernet (SGMII) (PA driver from PA clk) 4 = PCI 5 = I 6 = SPI 7 = HyperLink End of Table 2-3 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 31: Device Configuration Field

    Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 32: Figure 2-5 Ethernet (Sgmii) Device Configuration Fields

    PCI Device Configuration Field Descriptions Field Description Reserved Reserved Bar Config PCIe BAR registers configuration This value can range from 0 to 0xf. See Table 2-8. Reserved Reserved End of Table 2-7 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 33: Table 2-9 I 2 C Master Mode Device Configuration Field Descriptions

    ‘‘I2C Passive Mode’’) Parameter Index Identifies the index of the configuration table initially read from the I C EEPROM. This value can range from 0 to 32. End of Table 2-9 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 34: Table 2-10 I 2 C Passive Mode Device Configuration Field Descriptions

    0 = 16-bit address values are used 1 = 24-bit address values are used Chip Select The chip select field value Parameter Table Index Specifies which parameter table is loaded End of Table 2-11 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 35: Pll Settings

    128. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Table 2-13 C66x CorePac System PLL Configuration...

  • Page 36: Second-Level Bootloaders

    8 10 12 14 16 18 20 22 24 26 28 2.6.2 Pin Map Figure 2-13 through Figure 2-16 show the TMS320C6670 pin assignments in four quadrants (A, B, C, and D). Figure 2-12 Pin Map Quadrants (Bottom View) Device Overview Copyright 2012 Texas Instruments Incorporated...

  • Page 37: Figure 2-13 Upper Left Quadrant—A (Bottom View)

    VDDT1 CVDD CVDD CVDD1 CVDD1 FLDAT MCMREF MCMREF MCMRX RSV14 DVDD18 VDDT1 CVDD CVDD CVDD CVDD CLKOUTN CLKOUTP FLCLK CVDD CVDD CVDD CVDD MCMRXN0 MCMTXN0 VDDT1 CVDD CVDD CVDD CVDD Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 38: Figure 2-14 Upper Right Quadrant—B (Bottom View)

    CVDD1 CVDD CVDD CVDD AVDDA1 RSV05 CVDD CVDD CVDD CVDD VDDT3 AIFTXP5 AIFRXP5 CVDD CVDD CVDD CVDD VDDT3 RSV26 AIFTXN5 AIFTXN4 AIFRXN5 AIFRXP4 CVDD CVDD CVDD VDDT3 VDDT3 AIFTXP4 AIFRXN4 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 39: Figure 2-15 Lower Right Quadrant—C (Bottom View)

    DDRDQM1 DDRDQS0P DDRDQS0N DDRCLK DDRCB06 DDRDQS8N DDRCB03 DDRDQS3N DDRD30 DDRD21 DDRDQS2N DDRD14 DDRDQS1N DDRD05 DVDD15 OUTN1 DDRCLK DVDD15 DDRCB07 DDRDQS8P DDRDQM8 DDRDQS3P DDRDQM3 DDRD20 DDRDQS2P DDRDQM2 DDRD15 DDRDQS1P DVDD15 OUTP1 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 40: Figure 2-16 Lower Left Quadrant—D (Bottom View)

    DDRCLK DVDD15 DDRDQM7 DDRDQS6P DDRD50 DDRDQM6 DDRDQS5P DDRD44 DDRD38 DDRDQS4N DDRD34 DDRBA1 DDRA01 DDRA06 OUTN0 DDRCLK DVDD15 DDRDQS6N DDRD51 DDRD49 DDRDQS5N DDRD40 DDRDQM5 DDRDQS4P DDRDQM4 DVDD15 DDRBA0 DDRA00 DDRA04 OUTP0 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 41: Terminal Functions

    IPD/IPU. For more detailed information on pulldown/pullup resistors and IPD or IPU IPD/IPU situations in which external pulldown/pullup resistors are required, see the Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66. Analog signal Type Ground Type...
  • Page 42 PCIe module enable (pin shared with TIMI0) Clock / Reset SYSCLKP AC29 System clock input to antenna interface and/or main PLL SYSCLKN AC28 PASSCLKP AJ18 Network coprocessor reference clock to PASS PLL PASSCLKN AH18 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 43 DDR interface drivers to 50 Ohms. Presently, the recommended value for this 1% resistor is 45.3 Ohms. DDRDQM0 DDRDQM1 DDRDQM2 DDRDQM3 DDRDQM4 DDR EMIF data masks DDRDQM5 DDRDQM6 DDRDQM7 DDRDQM8 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 44 DDRDQS2P DDRDQS2N DDRDQS3P DDRDQS3N DDRDQS4P DDR EMIF data strobe DDRDQS4N DDRDQS5P DDRDQS5N DDRDQS6P DDRDQS6N DDRDQS7P DDRDQS7N DDRDQS8P DDRDQS8N DDRCB00 DDRCB01 DDRCB02 DDRCB03 DDR EMIF check bits DDRCB04 DDRCB05 DDRCB06 DDRCB07 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 45 DDRD04 DDRD05 DDRD06 DDRD07 DDRD08 DDRD09 DDRD10 DDRD11 DDRD12 DDRD13 DDRD14 DDR EMIF data bus DDRD15 DDRD16 DDRD17 DDRD18 DDRD19 DDRD20 DDRD21 DDRD22 DDRD23 DDRD24 DDRD25 DDRD26 DDRD27 DDRD28 DDRD29 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 46 DDRD47 DDRD48 DDRD49 DDRD50 DDRD51 DDRD52 DDRD53 DDRD54 DDRD55 DDRD56 DDRD57 DDRD58 DDRD59 DDRD60 DDRD61 DDRD62 DDRD63 DDRCE0 DDR EMIF chip enables DDRCE1 DDRBA0 DDRBA1 DDR EMIF bank address DDRBA2 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 47 DDR EMIF on-die termination outputs used to set termination on the SDRAMs DDRODT1 DDR reset signal DDRRESET DDRSLRATE0 Down DDR slew rate control DDRSLRATE1 Down Reference voltage input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2) VREFSSTL Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 48 These GPIO pins have secondary functions assigned to them as mentioned in the Boot GPIO08 AJ19 Down Configuration Pins section above. GPIO09 AE21 Down GPIO10 AG19 Down GPIO11 AD20 Down GPIO12 AE20 Down GPIO13 AF21 Down GPIO14 AH20 Down GPIO15 AD21 Down Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 49 JTAG clock input AD29 JTAG data input AD28 JTAG data output AC27 JTAG test mode input AC26 JTAG reset TRST AD26 Down MDIO MDIO data MDIO AG16 MDIO clock MDCLK AF16 Down Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 50 Ethernet MAC SGMII receive data (2 links) SGMII1RXN SGMII1RXP SGMII0TXN SGMII0TXP Ethernet MAC SGMII transmit data (2 links) SGMII1TXN SGMII1TXP SmartReflex VCNTL0 VCNTL1 Voltage control outputs to variable core power supply VCNTL2 VCNTL3 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 51 RSV22 AE16 Down Reserved - leave unconnected RSV23 AD16 Reserved - leave unconnected RSV24 AG17 Reserved - leave unconnected RSV25 AF17 Reserved - leave unconnected RSV26 Reserved - leave unconnected Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 52: Table 2-16 Terminal Functions - Power And Ground

    AD10, AD12, AD14, AD24, AD27, AE1, AE3, AE7, AE9, AE13, AF2, AF5, AF8, AF11, AF14, AF15, AF20, AG1, AG3, AG6, AG9, AG12, AG15, AG22, AG26, AH2, AH5, AH8, AH11, AH14, AJ1, AJ3, AJ6, AJ9, AJ12, AJ15, AJ29 End of Table 2-16 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 53 DDRA09 DDRD13 BOOTMODE06 † AH19 DDRA10 DDRD14 BOOTMODE07 † AJ19 DDRA11 DDRD15 BOOTMODE08 † AE21 DDRA12 DDRD16 BOOTMODE09 † AG19 DDRA13 DDRD17 BOOTMODE10 † AD20 DDRA14 DDRD18 BOOTMODE11 † AE20 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 54 D5, D8, D20, D23, E3, F5, F7, F9, F11, DDRD58 GPIO15 AD21 F17, F19, F27, G2, DDRD59 G4, G8, G10, G12, HOUT AC18 G14, G16 G18, G20, DDRD60 LENDIAN AJ20 † G22, G24 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 55 PCIECLKN AJ17 RSV04 SPISCS1 AJ22 PCIECLKP AH17 RSV05 SRIOSGMIICLKN AH16 PCIERXN0 AJ14 RSV06 SRIOSGMIICLKP AJ16 PCIERXN1 AH12 RSV07 SYSCLKN AC28 PCIERXP0 AJ13 RSV08 SYSCLKOUT AA26 PCIERXP1 AH13 RSV09 SYSCLKP AC29 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 56 H20, H22, J1, J3, J5, AJ15, AJ29 J7, J9, J11, J13, J15, End of Table 2-17 J17, J19, J21, J27, J29, K1, K2, K3, K4, K5, K8, K10, K12, K14, K16, K18, K20 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...

  • Page 57: Table 2-18 Terminal Functions - By Ball Number

    DDRA13 DDRD01 DDRDQS6P DDRA15 DDRD62 DDRD50 DDRCB05 DDRD58 DDRDQM6 DDRCB04 DVDD15 DDRDQS5P DDRCB01 DDRD53 DDRD44 DDRD29 DDRD38 DDRD31 DDRD45 DDRDQS4N DDRD42 DDRD34 DDRD22 DDRD39 DVDD15 DDRD36 DDRCLKOUTN0 DDRD13 DDRD32 DDRBA1 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 58 CVDD1 DVDD15 DVDD15 CVDD1 DVDD15 DVDD15 CVDD1 DDRA03 RSV21 CVDD1 DDRA02 RSV19 DDRA08 DVDD18 CVDD DDRCLKP DVDD15 CVDD1 CVDD1 DVDD15 CVDD1 CVDD1 DDRD25 DDRD27 CVDD1 CVDD DDRD17 DDRD16 CVDD1 CVDD1 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 59 CVDD1 MCMRXP2 CVDD MCMRXP3 CVDD CVDD MCMTXP2 CVDD1 MCMTXN3 CVDD RSV0B VDDT1 CVDD RSV0A VDDT3 CVDD1 CVDD AIFTXP1 CVDD VDDT3 VDDR6 AIFRXN1 CVDD MCMRXN2 AIFTXP3 CVDD AIFRXP3 MCMTXN2 CVDD MCMRXN1 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 60 AIFRXN3 CVDD AIFTXN5 MCMRXP1 AIFTXN4 MCMRXP0 CVDD AIFRXN5 AIFRXP4 MCMTXN1 CVDD MCMREFCLKOUTN MCMTXP0 MCMREFCLKOUTP VDDT1 CVDD MCMRXFLCLK RSV14 CVDD CVDD DVDD18 CVDD VDDT3 VDDT1 CVDD VDDT3 CVDD CVDD AIFTXP4 CVDD Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 61 AB10 CVDD1 RSV04 AB11 RP1CLKP AB12 CVDD1 RP1FBP AB13 MCMTXPMDAT AB14 CVDD MCMTXPMCLK AB15 AVDDA3 MCMRXPMCLK AB16 CVDD VCNTL2 AB17 DVDD18 AB18 CVDD AB19 DVDD18 AB20 AVDDA1 CVDD AB21 DVDD18 Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 62 AF18 † BOOTMODE03 AC29 SYSCLKP AE10 VDDT2 AF19 DVDD18 CVDD1 AE11 VDDR4 AF20 AE12 VDDT2 AF21 GPIO13 CVDD1 AE13 AF21 † BOOTMODE12 AE14 RSV16 AF22 DVDD18 VDDT2 AE15 VDDR2 AF23 TIMO1 Copyright 2012 Texas Instruments Incorporated Device Overview Submit Documentation Feedback...
  • Page 63 TIMI1 SGMII1RXP AG24 UARTRTS AG25 EMU13 RIORXN2 AG26 RIORXP2 AG27 EMU12 AG28 EMU11 AJ10 RIORXP0 AG29 EMU09 AJ11 RIORXN0 CVDD1 AJ12 AJ13 PCIERXP0 SGMII0RXN AJ14 PCIERXN0 SGMII0RXP AJ15 AJ16 SRIOSGMIICLKP Device Overview Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 64: Development

    Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

  • Page 65: Figure 2-17 C66X™ Dsp Device Nomenclature (Including The Tms320C6670 Dsp)

    CYP), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]). For device part numbers and further ordering information for TMS320C6670 in the CYP package type, see the TI website www.ti.com...

  • Page 66: Related Documentation From Texas Instruments

    Multicore Fixed and Floating-Point System-on-Chip SPRS689D—March 2012 www.ti.com 2.9 Related Documentation from Texas Instruments These documents describe the TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip. Copies of these documents are available on the Internet at www.ti.com 64-bit Timer (Timer 64) for KeyStone Devices User Guide...

  • Page 67: Device Configuration

    3 Device Configuration On the TMS320C6670 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.

  • Page 68: Peripheral Selection After Device Reset

    PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 3.3 Device State Control Registers The TMS320C6670 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-2.
  • Page 69 Device State Control Registers (Part 2 of 4) Address Start Address End Size Acronym Description 0x02620150 0x02620153 PWRSTATECTL See section 3.3.10 0x02620154 0x02620157 SRIO_SERDES_STS ‘‘Related Documentation from Texas Instruments’’ on page 66 0x02620158 0x0262015B SGMII_SERDES_STS 0x0262015C 0x0262015F PCIE_SERDES_STS 0x02620160 0x02620160 HYPERLINK_SERDES_STS 0x02620164 0x02620167 AIF2_A_SERDES_STS...
  • Page 70 0x02620337 DDR3PLLCTL1 0x02620338 0x0262033B PASSPLLCTL0 See section 7.7 ‘‘PASS PLL’’ on page 144 0x0262033C 0x0262033F PASSPLLCTL1 0x02620340 0x02620343 SGMII_SERDES_CFGPLL ‘‘Related Documentation from Texas Instruments’’ on page 66 0x02620344 0x02620347 SGMII_SERDES_CFGRX0 0x02620348 0x0262034B SGMII_SERDES_CFGTX0 0x0262034C 0x0262034F SGMII_SERDES_CFGRX1 0x02620350 0x02620353 SGMII_SERDES_CFGTX1 0x02620354...

  • Page 71: Device Status (Devstat) Register

    SPRS689D—March 2012 www.ti.com Table 3-2 Device State Control Registers (Part 4 of 4) Address Start Address End Size Acronym Description 0x02620374 0x02620377 SRIO_SERDES_CFGRX2 ‘‘Related Documentation from Texas Instruments’’ on page 66 0x02620378 0x0262037B SRIO_SERDES_CFGTX2 0x0262037C 0x0262037F SRIO_SERDES_CFGRX3 0x02620380 0x02620383 SRIO_SERDES_CFGTX3 0x02620384...

  • Page 72: Device Configuration Register

    30 and see the Bootloader for the C66x DSP User Guide in2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66. LENDIAN Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little endian mode (default).

  • Page 73: Jtag Id (Jtagid) Register Description

    11-1 MANUFACTURER 0000 0010 111b Manufacturer This bit is read as a 1 for TMS320C6670 End of Table 3-5 The value of the VARIANT and PART NUMBER fields depend on the silicon revision being used. Note— See the Silicon Errata for details.

  • Page 74: Lresetnmi Pin Status Clear (Lrstnmipinstat_Clr) Register

    CorePac0 in NMI Clear 15-4 Reserved Reserved CorePac3 in Local Reset Clear CorePac2 in Local Reset Clear CorePac1 in Local Reset Clear CorePac0 in Local Reset Clear End of Table 3-7 Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 75: Reset Status (Reset_Stat) Register

    Reset Status Clear Register (RESET_STAT_CLR) Reserved RW, +0 R, + 000 0000 0000 0000 0000 0000 0000 RW,+0 RW,+0 RW,+0 RW,+0 Legend: R = Read only; RW = Read/Write; -n = value after reset Copyright 2012 Texas Instruments Incorporated Device Configuration Submit Documentation Feedback...

  • Page 76: Boot Complete (Bootcomplete) Register

    CorePac2 boot status 0 = CorePac2 boot NOT complete 1 = CorePac2 boot complete CorePac1 boot status 0 = CorePac1 boot NOT complete 1 = CorePac1 boot complete End of Table 3-10 Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 77: Power State Control (Pwrstatectl) Register

    Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User Guide in2.9 ‘‘Related Documentation from Texas Instruments’’ on page HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.

  • Page 78: Ipc Generation (Ipcgrx) Registers

    1 = Sets both SRCSx and the corresponding SRCCx. Reserved Reserved IPCG Reads return 0. Writes: 0 = No effect 1 = Creates an inter-DSP interrupt. End of Table 3-13 Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 79: Ipc Acknowledgement (Ipcarx) Registers

    RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0 Legend: R = Read only; RW = Read/Write; -n = value after reset Copyright 2012 Texas Instruments Incorporated Device Configuration Submit Documentation Feedback...

  • Page 80: Ipc Acknowledgement Host (Ipcarh) Register

    RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +1 RW, +1 RW, +0 Legend: R = Read only; RW = Read/Write; -n = value after reset Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 81 1 = TIMI1 TINPHSEL0 Input select for TIMER0 high. 0 = TIMI0 1 = TIMI1 TINPLSEL0 Input select for TIMER0 low. 0 = TIMI0 1 = TIMI1 End of Table 3-17 Copyright 2012 Texas Instruments Incorporated Device Configuration Submit Documentation Feedback...

  • Page 82: Timer Output Selection Register (Toutpsel)

    1001: TOUTH4 0010: TOUTL1 1010: TOUTL5 0011: TOUTH1 1011: TOUTH5 0100: TOUTL2 1100: TOUTL6 0101: TOUTH2 1101: TOUTH6 0110: TOUTL3 1110: TOUTL7 0111: TOUTH3 1111: TOUTH7 End of Table 3-18 Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 83: Reset Mux (Rstmuxx) Register

    111b = Reserved LOCK Lock register fields 0 = Register fields are not locked (default) 1 = Register fields are locked until the next timer reset End of Table 3-19 Copyright 2012 Texas Instruments Incorporated Device Configuration Submit Documentation Feedback...

  • Page 84: Device Speed (Devspeed) Register

    0b0000 0001 x = 1200 MHz 0b001x xxxx x = 1200 MHz 0b01xx xxxx x = 1000 MHz 0b1xxx xxxx x = 800 MHz 22-0 Reserved Reserved. Read only End of Table 3-20 Device Configuration Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 85: Pullup/Pulldown Resistors

    For more detailed information on input current (I ), and the low-level/high-level input voltages (V and V ) for the TMS320C6670 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 107. To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-16 ‘‘Terminal...

  • Page 86: System Interconnect

    4 System Interconnect On the TMS320C6670 device, the C66x CorePacs, the EDMA3 transfer controllers, and the system peripherals are interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free internal data movement. The TeraNet provides low-latency, concurrent data transfers between master peripherals and slave peripherals.

  • Page 87: Switch Fabric Connections Matrix

    EDMA3CC0_TC1_RD EDMA3CC0_TC1_WR EDMA3CC1_TC0_RD EDMA3CC1_TC0_WR EDMA3CC1_TC1_RD EDMA3CC1_TC1_WR EDMA3CC1_TC2_RD EDMA3CC1_TC2_WR EDMA3CC1_TC3_RD EDMA3CC1_TC3_WR EDMA3CC2_TC0_RD EDMA3CC2_TC0_WR EDMA3CC2_TC1_RD EDMA3CC2_TC1_WR EDMA3CC2_TC2_RD EDMA3CC2_TC2_WR EDMA3CC2_TC3_RD EDMA3CC2_TC3_WR SRIO Packet DMA SRIO_Master PCIe_Master Network Coprocessor Packet DMA MSMC_Data_Master QM_SS_Master QM_SS_Second Copyright 2012 Texas Instruments Incorporated System Interconnect Submit Documentation Feedback...

  • Page 88: Table 4-2 Switch Fabric Connection Matrix Section 2

    End of Table 4-1 Table 4-2 Switch Fabric Connection Matrix Section 2 (Part 1 of 2) Slave Masters HyperLink_Master BCP_FFTCC_TCP3dC Master EDMA3CC0_TC0_RD EDMA3CC0_TC0_WR EDMA3CC0_TC1_RD EDMA3CC0_TC1_WR EDMA3CC1_TC0_RD EDMA3CC1_TC0_WR EDMA3CC1_TC1_RD EDMA3CC1_TC1_WR EDMA3CC1_TC2_RD EDMA3CC1_TC2_WR EDMA3CC1_TC3_RD System Interconnect Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 89: Table 4-3 Switch Fabric Connection Matrix Section 3

    Switch Fabric Connection Matrix Section 3 (Part 1 of 2) Slave Masters RAC_CFG FFTC_CFG TAC_CFG TCP3e_CFG TCP3d_CFG VCP2_CFG AIF2_CFG UART_CFG HyperLink_Master 1, 12 1, 12 1, 12 1, 12 1, 12 BCP_FFTCC_TCP3dC Master EDMA3CC0_TC0_RD Copyright 2012 Texas Instruments Incorporated System Interconnect Submit Documentation Feedback...
  • Page 90 SRIO Packet DMA SRIO_M PCIe_Master Network Coprocessor Packet DMA MSMC_Data_Master QM_SS Packet DMA QM_SS Second DebugSS_Master FFTC RAC_BE0 RAC_BE1 AIF_Master TAC_FE EDMA3CC0 EDMA3CC1 EDMA3CC2 CorePac0_CFG CorePac1_CFG CorePac2_CFG CorePac3_CFG End of Table 4-3 System Interconnect Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 91: Teranet Switch Fabric Connections

    RAC_A_BE0 CPU/3 Boot_ROM RAC_B_BE1 Bridge_5 RAC_B_BE0 Bridge_6 TAC_FE Bridge_7 To TeraNet_2_A AIF/DMA Bridge_8 TC_0 Bridge_9 TC_1 EDMA TC_2 Bridge_10 TC_3 Bridge_12 TC_0 To TeraNet_3P_A TC_1 Bridge_13 EDMA TC_2 Bridge_14 TC_3 Copyright 2012 Texas Instruments Incorporated System Interconnect Submit Documentation Feedback...

  • Page 92: Figure 4-2 Teranet 2A

    From TeraNet 2M MSMC DDR3 Bridge_5 Bridge_6 Tracer_MSMC0 Bridge_7 Tracer_MSMC1 From TeraNet_3_A Bridge_8 Tracer_MSMC2 Bridge_9 Tracer_MSMC3 Bridge_10 Tracer_DDR HyperLink HyperLink To TeraNet 2A TC_0 EDMA TC_1 Bridge_1 Bridge_2 To TeraNet_3_A Bridge_3 Bridge_4 System Interconnect Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 93: Figure 4-3 Teranet 3P And 3M And 2M

    SPRS689D—March 2012 www.ti.com Figure 4-3 TeraNet 3P and 3M and 2M FFTC_ Packet DMA BCP_ Packet DMA To TeraNet 2A BCP_DIO0 BCP_DIO1 From TeraNet 2A TCP3d_DMA MPU_CFG TCP3D_CFG FFTC_CFG BCP_CFG Copyright 2012 Texas Instruments Incorporated System Interconnect Submit Documentation Feedback...

  • Page 94: Figure 4-4 Teranet 3P_A

    TETB (Debug_SS) CorePac_3 × TETB (core) ( 4) RAC_A_CFG TNet_3P_H MPU_4 CPU/3 RAC_B_CFG Tracer_RAC_CFG To TeraNet_3P_Tracer MPU_0 To TeraNet_3P_B Tracer_CFG n indicates the number of MPUs present in the specific device. System Interconnect Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 95: Figure 4-5 Teranet 3P_B

    Tracer From TeraNet_3P_A × × ( 11 / 12) SRIO NETCP VCP2 VCP2 TNet_3P_E CPU/3 VCP2 VCP2 AIF2 TCP3d_A TNet_3P_F CPU/3 TCP3d_B TCP3e FFTC_A TNet_3P_G CPU/3 FFTC_B To TeraNet_6P_B Bridge_20 Copyright 2012 Texas Instruments Incorporated System Interconnect Submit Documentation Feedback...

  • Page 96: Figure 4-6 Teranet 6P_B And 3P_Tracer

    Tracer_ QM_P Tracer_L2_ 0 to 3 Tracer_RAC Tracer_TAC Tracer_ RAC_CFG SmartReflex Bridge_20 GPIO From TeraNet_3P_B UART BOOTCFG PLL_CTL Debug_SS × × CIC ( 3 / 4) × Timer ( 8) System Interconnect Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 97: Bus Priorities

    Control the priority level for the transactions from packet DMA master port, which access the external linking RAM. End of Table 4-4 For all other modules, see the respective User Guides in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 for programmable priority registers.

  • Page 98: C66X Corepac

    B31-B16 A15-A0 B15-B0 DMA Switch GPSC Fabric Data Memory Controller (DMC) With CFG Switch Memory Protect/Bandwidth Mgmt Fabric 32KB L1D Cores 1 & 2 Cores 1 & 2 only only C66x CorePac Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 99: Memory Architecture

    2.9 ‘‘Related Documentation from Texas Instruments’’ on page 5.1 Memory Architecture Each CorePac of the TMS320C6670 device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 2048KB multicore shared memory (MSM).

  • Page 100: L1D Memory

    00F0 0000h 16K bytes SRAM SRAM SRAM 2-Way 00F0 4000h Cache SRAM 8K bytes 2-Way 00F0 6000h Cache 4K bytes 2-Way 00F0 7000h Cache 2-Way 4K bytes Cache 00F0 8000h C66x CorePac Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 101: L2 Memory

    256K bytes 4-Way 008C 0000h Cache 128K bytes 4-Way 008E 0000h Cache 64K bytes 4-Way 008F 0000h Cache 32K bytes 4-Way 008F 8000h Cache 32K bytes 4-Way 008F FFFFh Cache Copyright 2012 Texas Instruments Incorporated C66x CorePac Submit Documentation Feedback...

  • Page 102: Msm Sram

    Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 5.1.5 L3 Memory The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

  • Page 103: Bandwidth Management

    PRI_ALLOC have their own registers to program their priorities. More information on the bandwidth management features of the CorePac can be found in the C66x CorePac Reference Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66. Copyright 2012 Texas Instruments Incorporated C66x CorePac...

  • Page 104: Power-Down Control

    More information on the power-down features of the C66x CorePac can be found in the C66x CorePac Reference Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 5.5 CorePac Revision The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID) located at address 0181 2000h.

  • Page 105: Device Operating Conditions

    6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8V LVCMOS signals is DVDD18 + 0.20 DVDD18 and × maximum undershoot value would be V - 0.20 DVDD18 Copyright 2012 Texas Instruments Incorporated Device Operating Conditions Submit Documentation Feedback...

  • Page 106: Recommended Operating Conditions

    3 SRVnom refers to the unique SmartReflex core supply voltage between 0.9 V and 1.1 V set from the factory for each individual device. 4 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind. Device Operating Conditions Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 107: Electrical Characteristics

    (Hi-Z) output leakage current. C uses open collector IOs and does not have a I OH Maximum. applies to output-only pins, indicating off-state (Hi-Z) output leakage current. Copyright 2012 Texas Instruments Incorporated Device Operating Conditions Submit Documentation Feedback...

  • Page 108: Power Supply To Peripheral I/O Mapping

    1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers. 2 Please see the Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 for more information about individual peripheral I/O.

  • Page 109: Tms320C6670 Peripheral Information And Electrical Specifications

    7 TMS320C6670 Peripheral Information and Electrical Specifications This chapter covers the various peripherals on the TMS320C6670 device. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter. 7.1 Recommended Clock and Control Signal Transition Behavior...

  • Page 110: Power-Up Sequencing

    RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock that is used by the CorePac, see Figure 7-7 for more details. TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 111: Figure 7-1 Core Before Io Power Sequencing

    7.2.1.1 Core-Before-IO Power Sequencing Figure 7-1 shows the power sequencing and reset control of the TMS320C6670 for device initialization. POR may be removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after the rising edge of POR, but may be held low for longer periods if necessary.
  • Page 112 • GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL End of Table 7-2 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 113: Figure 7-2 Io Before Core Power Sequencing

    Figure 7-2 IO Before Core Power Sequencing Power Stabilization Phase Device Initialization Phase RESETFULL GPIO Config Bits RESET CVDD CVDD1 DVDD18 DVDD15 SYSCLK1P&N DDRCLKP&N RESETSTAT Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 114 CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the other connected to CVDD. TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated...

  • Page 115: Power-Down Sequence

    For recommendations on selection of power supply decoupling and bulk capacitors see the Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 116: Smartreflex

    To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required to be implemented whenever the TMS320C6670 device is used. The voltage selection is done using 4 VCNTL pins which are used to select the output voltage of the core voltage regulator.

  • Page 117: Power Sleep Controller (Psc)

    For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 7.3.1 Power Domains The device has several power domains that can be turned on for operation or off to minimize power dissipation. The global power/sleep controller (GPSC) is used to control the power gating of various power domains.

  • Page 118: Clock Domains

    TCP3d_B Software control BCP, FFTC_C, and TCP3d_C Software control No LPSC Bootcfg, PSC, and PLL Controller These modules do not use LPSC End of Table 7-7 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 119: Psc Register Memory Map

    PDCTL10 Power Domain Control Register 10 (AIF2) 0x32C PDCTL11 Power Domain Control Register 11 (TCP3d_A) 0x330 PDCTL12 Power Domain Control Register 12 (VCP2_B, VCP2_C and VCP2_D) Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 120 Module Control Register 1 (SmartReflex) 0xA08 MDCTL2 Module Control Register 2 (DDR3 EMIF) 0xA0C MDCTL3 Module Control Register 3 (TCP3e) 0xA10 MDCTL4 Module Control Register 4 (VCP2_A) TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 121 Module Control Register 28 (C66x CorePac3 and Timer 3) 0xA74 MDCTL29 Module Control Register 29 (TCP3d_B) 0xA78 MDCTL30 Module Control Register 30(BCP, FFTC_C and TCP3d_C) 0xA7C - 0xFFC Reserved Reserved End of Table 7-8 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 122: Reset Controller

    Multicore Fixed and Floating-Point System-on-Chip SPRS689D—March 2012 www.ti.com 7.4 Reset Controller The reset controller detects the different type of resets supported on the TMS320C6670 device and manages the distribution of those resets throughout the device. The device has the following types of resets: •...

  • Page 123: Hard Reset

    The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR Note— is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied to the POR pin. Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 124: Soft Reset

    The local reset can be used to reset a particular CorePac without resetting any other device components. Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66): •...

  • Page 125: Reset Priority

    131. For more details on these registers and how to program them, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66. Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 126: Reset Electrical Data/Timing

    End of Table 7-11 1 C = 1/SYSCLK1 clock frequency in ns Figure 7-4 RESETFULL Reset Timing RESETFULL RESET RESETSTAT Figure 7-5 Soft/Hard Reset Timing RESETFULL RESET RESETSTAT TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 127: Table 7-12 Boot Configuration Timing Requirements

    Hold time - GPIO valid after RESETFULL asserted End of Table 7-12 1 C = 1/SYSCLK1 clock frequency in ns. Figure 7-6 Boot Configuration Timing RESETFULL GPIO[15:0] Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 128: Main Pll And The Pll Controller

    SYSCLK2 PLLEN PLLDIV3 SYSCLK3 PLLENSRC PLLDIV4 SYSCLK4 PLLDIV5 SYSCLK5 PLLDIV6 SYSCLK6 To Switch Fabric, Peripherals, Accelerators PLLDIV7 SYSCLK7 PLLDIV8 SYSCLK8 PLLDIV9 SYSCLK9 PLLDIV10 SYSCLK10 PLLDIV11 SYSCLK11 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 129: Main Pll Controller Device-Specific Information

    ‘‘Related Documentation from Texas Instruments’’ on page 66 includes a superset of features, some of which are not supported on the TMS320C6670 device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device.

  • Page 130: Table 7-13 Main Pll Stabilization, Lock, And Reset Times

    SYSCLK10: 1/3-rate clock for SRIO only. • SYSCLK11: 1/6-rate clock for PSC only. Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on the TMS320C6670 device. In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8 Note—...

  • Page 131: Pll Controller Memory Map

    Loop (PLL) Controller for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Note that only registers documented here are accessible on the TMS320C6670. Other addresses CAUTION— in the PLL Controller memory map including the Reserved registers should not be modified. Furthermore, only the bits within the registers described here are supported.

  • Page 132: Table 7-15 Pll Secondary Control Register Field Descriptions

    0h = ÷1. Divide frequency by 1 1h = ÷2. Divide frequency by 2 2h - Fh = Reserved 18-0 Reserved Reserved End of Table 7-15 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 133: Table 7-16 Pll Controller Divider Register Field Descriptions

    1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn. End of Table 7-17 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 134: Table 7-18 Plldiv Divider Ratio Change Status Register Field Descriptions

    End of Table 7-19 1 Where N = 1, 2, 3,..N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual) TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated...

  • Page 135: Table 7-20 Reset Type Status Register Field Descriptions

    Power-on reset 0 = Power-on reset was not the last reset to occur 1 = Power-on reset was the last reset to occur End of Table 7-20 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 136: Table 7-21 Reset Control Register Field Descriptions

    PLL controller initiates a software-driven reset of type: 0 = Hard reset (default) 1 = Soft reset RESETTYPE RESET initiates a reset of type: 0 = Hard reset (default) 1 = Soft reset TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 137: Table 7-23 Reset Isolation Register Field Descriptions

    MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module. For more information on the MDCTLx Register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66. The Reset Isolation register (RSTCTRL) is...

  • Page 138: Main Pll Control Registers

    PLLM[12:0] value (round down if PLLM has an odd value) Example: If PLLM = 15, then BWADJ = 7 End of Table 7-25 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 139: Main Pll And Pll Controller Initialization Sequence

    Transition time ALTCORECLKP rise time (250 mV) tf(ALTCORECLKP_250 mv) Transition time ALTCORECLKP fall time (250 mV) tj(ALTCORECLKN) Jitter, peak_to_peak _ periodic ALTCORECLKN tj(ALTCORECLKP) Jitter, peak_to_peak _ periodic ALTCORECLKP Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 140 Transition time PCIECLKN rise time (250 mV) tf(PCIECLKN_250mv) Transition time PCIECLKN fall time (250 mV) tr(PCIECLKP_250mv) Transition time PCIECLKP rise time (250 mV) tf(PCIECLKP_250mv) Transition time PCIECLKP fall time (250 mV) TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 141: Figure 7-19 Main Pll Controller/Srio/Hyperlink/Pcie Clock Input Timing

    End of Table 7-26 1 See the Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 for detailed recommendations. 2 If AIF2 is being used then SYSCLK(N|P) can be programmed only to fixed values, if AIF2 is not being used then any value in the range between the min and max values can be used.

  • Page 142: Ddr3 Pll

    Reserved PLLM PLLD RW,+0000 1001 RW,+0 RW,+0001 RW,+0000000010011 RW,+000000 Legend: RW = Read/Write; -n = value after reset 1 This register is Reset on POR only TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 143: Ddr3 Pll Device-Specific Information

    2. In DDR3PLLCTL0, write BYPASS = 1 (set the PLL in Bypass) 3. In DDR3PLLCTL1, write PLLRST = 1 (PLL is reset) 4. Program PLLM and PLLD in DDR3PLLCTL0 register Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 144: Ddr3 Pll Input Clock Electrical Data/Timing

    PASS PLL comes out in a bypass mode and needs to be programmed to a valid frequency before being enabled and used. TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 145: Pass Pll Control Registers

    PLL supplies. Please see the Hardware Design Guide for KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown.

  • Page 146: Pass Pll Device-Specific Information

    PASS PLL. 1. In PASSPLLCTL1, write ENSAT = 1 (for optimal PLL operation) 2. In PASSPLLCTL0, write BYPASS = 1 (set the PLL in Bypass) TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 147: Pass Pll Input Clock Electrical Data/Timing

    Transition time _ PASSCLKP fall time (250 mV) tj(PASSCLKN) Jitter, peak_to_peak _ periodic PASSCLKN ps, pk-pk tj(PASSCLKP) Jitter, peak_to_peak _ periodic PASSCLKP ps, pk-pk Figure 7-28 PASS PLL Timing PASSCLKN PASSCLKP Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 148: Enhanced Direct Memory Access (Edma3) Controller

    Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, four transfer controllers and four event queues with programmable system-level priority for each of EDMA3CC1 and EDMA3CC2 • Interrupt generation for transfer completion and error conditions TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 149: Edma3 Device-Specific Information

    VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page For the range of memory addresses that include EDMA3 channel controller (EDMA3CC) control registers and EDMA3 transfer controller (EDMA3TC) control register see Section 2.2...

  • Page 150: Edma3 Channel Synchronization Events

    For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Table 7-35 EDMA3CC0 Events for C6670...
  • Page 151 TAC error interrupt TACDEVENT0 TAC debug event TACDEVENT1 TAC debug event RAC_BINT0 RAC_B_ interrupt 0 RAC_BINT1 RAC_B_ interrupt 1 RAC_BINT2 RAC_B_interrupt 2 RAC_BINT3 RAC_B_interrupt 3 RAC_BDEVENT0 RAC_B_debug Event Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 152 Transmit event VCPBREVT Receive event VCPBXEVT Transmit event VCPCREVT Receive event VCPCXEVT Transmit event VCPDREVT Receive event VCPDXEVT Transmit event SEMINT0 Semaphore interrupt SEMINT1 Semaphore interrupt TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 153 Interrupt Controller output TCP3D_C_REVT0 TCP3d_C Receive event0 TCP3D_C_REVT1 TCP3d_C Receive event1 FFTC_C_ERROR0 FFTC_C Error event and FFTC_C debug event FFTC_C_ERROR1 FFTC_C Error event and FFTC_C debug event Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 154 EDMA3CC2 Events for C6670 (Part 3 of 3) Event Number Event Event Description FFTC_C_ERROR2 FFTC_C Error event and FFTC_C debug event FFTC_C_ERROR3 FFTC_C Error event and FFTC_C debug event End of Table 7-37 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 155: Interrupts

    C66x CorePac. For more details on the CIC features, please see the Chip Interrupt Controller (CIC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Modules such as FFTC, TCP3d, TCP3e, TAC, AIF, CP_MPU, BOOT_CFG, and Tracer have level Note—...

  • Page 156: Table 7-38 System Event Mapping - C66X Corepac Primary Interrupts

    For more information on the Interrupt Controller, see the C66x CorePac User Guide in2.9 ‘‘Related Documentation from Texas Instruments’’ on page Table 7-38 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
  • Page 157 QM interrupt for 256~287 queues QM_INT_LOW_9 QM interrupt for 288~319 queues QM_INT_LOW_10 QM interrupt for 320~351 queues QM_INT_LOW_11 QM interrupt for 352~383 queues QM_INT_LOW_12 QM interrupt for 384~415 queues Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 158 Local GPIO interrupt GPINT9 Local GPIO interrupt GPINT10 Local GPIO interrupt GPINT11 Local GPIO interrupt GPINT12 Local GPIO interrupt GPINT13 Local GPIO interrupt GPINT14 Local GPIO interrupt TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 159 Core [n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn and TETBUNFLINTn. Core [n] will receive SEMINTn and SEMERRn. Core [n] will receive PCIEXpress_MSI_INTn and PCIEXpress_MSI_INTn+1. Core [n] will receive MSMC_mpf_errorn. Core [n] will receive GPINTn. Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 160: Table 7-39 Cic0 Event Inputs - C66X Corepac Secondary Interrupts

    EDMA3CC0 TC0 error interrupt EDMA3CC0 EDMATC_ERRINT1 EDMA3CC0 TC1 error interrupt EDMA3CC0 EDMACC_GINT EDMA3CC0 GINT Reserved EDMA3CC0 INT0 EDMA3CC0 individual completion interrupt EDMA3CC0 INT1 EDMA3CC0 individual completion interrupt TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 161 Tracer sliding time window interrupt for MSMC SRAM bank3 Tracer_CFG_INTD Tracer sliding time window interrupt for CFG0 SCR Tracer_QM_SS_CFG_INTD Tracer sliding time window interrupt for QM_SS CFG Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 162 RapidIO Interrupt INTDST3 RapidIO Interrupt INTDST4 RapidIO Interrupt INTDST5 RapidIO Interrupt INTDST6 RapidIO Interrupt INTDST7 RapidIO Interrupt INTDST8 RapidIO Interrupt INTDST9 RapidIO Interrupt INTDST10 RapidIO Interrupt TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 163 TCP3e read event TCP3EWEVT TCP3e write event TCP3D_BREVT0 TCP3d_B receive event0 TCP3D_BREVT1 TCP3d_B receive event1 UARTINT UART interrupt URXEVT UART receive event UTXEVT UART transmit event Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 164 RAC_B_debug Event TCP3D_C_REVT0 TCP3d_C receive event0 TCP3D_C_REVT1 TCP3d_C receive event1 FFTC_C_ERROR0 FFTC_C Error event and FFTC_C debug event FFTC_C_ERROR1 FFTC_C Error event and FFTC_C debug event TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 165: Table 7-40 Cic1 Event Inputs (Secondary Events For Edma3Cc1 And Edma3Cc2)

    QM interrupt QM_INT_HIGH_21 QM interrupt QM_INT_HIGH_22 QM interrupt QM_INT_HIGH_23 QM interrupt QM_INT_HIGH_24 QM interrupt QM_INT_HIGH_25 QM interrupt QM_INT_HIGH_26 QM interrupt QM_INT_HIGH_27 QM interrupt QM_INT_HIGH_28 QM interrupt Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 166 Correctable (1-bit) soft error detected on SRAM read MSMC_DEDC_NC_ERROR Non-correctable (2-bit) soft error detected on SRAM read MSMC_SCRUB_NC_ERROR Non-correctable (2-bit) soft error detected during scrub cycle Reserved TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 167 INTDST21 RapidIO interrupt INTDST22 RapidIO interrupt INTDST23 RapidIO interrupt AIF_INTD AIF CPU error interrupt and AIF CPU alarm interrupt and starvation interrupt Reserved VCPAINT Error interrupt Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 168 FFTC_A error event and FFTC_A debug event FFTC_B_INTD2 FFTC_B error event and FFTC_B debug event FFTC_B_INTD3 FFTC_B error event and FFTC_B debug event Reserved Reserved inputs End of Table 7-40 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 169: Table 7-41 Cic2 Event Inputs (Secondary Events For Edma3Cc0 And Hyperlink)

    Tracer sliding time window interrupt for QM_SS CFG TRACER_QM_SS_DMA_INTD Tracer sliding time window interrupt for QM_SS slave port TRACER_SEM_INTD Tracer sliding time window interrupt for Semaphore Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 170: Cic Registers

    Host Int Enable Set Index Register 0x38 HINT_ENABLE_CLR_INDEX_REG Host Int Enable Clear Index Register 0x200 RAW_STATUS_REG0 Raw Status Register 0 0x204 RAW_STATUS_REG1 Raw Status Register 1 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 171 Interrupt Channel Map Register for 60 to 60+3 0x440 CH_MAP_REG16 Interrupt Channel Map Register for 64 to 64+3 0x444 CH_MAP_REG17 Interrupt Channel Map Register for 68 to 68+3 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 172 Host Interrupt Map Register for 28 to 28+3 0x820 HINT_MAP_REG8 Host Interrupt Map Register for 32 to 32+3 0x824 HINT_MAP_REG9 Host Interrupt Map Register for 36 to 36+3 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 173 ENABLE_REG2 Enable Register 2 0x30c ENABLE_REG3 Enable Register 3 0x310 ENABLE_REG4 Enable Register 4 0x380 ENABLE_CLR_REG0 Enable Clear Register 0 0x384 ENABLE_CLR_REG1 Enable Clear Register 1 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 174 Interrupt Channel Map Register for 152 to 152+3 0x49c CH_MAP_REG39 Interrupt Channel Map Register for 156 to 156+3 0x800 HINT_MAP_REG0 Host Interrupt Map Register for 0 to 0+3 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 175 Interrupt Channel Map Register for 16 to 16+3 0x414 CH_MAP_REG5 Interrupt Channel Map Register for 20 to 20+3 0x418 CH_MAP_REG6 Interrupt Channel Map Register for 24 to 24+3 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 176: Inter-Processor Register Map

    IPC Generation Register for CorePac1 0x02620248 0x0262024B IPCGR2 IPC Generation Register for CorePac2 0x0262024C 0x0262024F IPCGR3 IPC Generation Register for CorePac3 0x02620250 0x02620253 Reserved Reserved 0x02620254 0x02620257 Reserved Reserved TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 177: Nmi And Lreset

    De-assert local reset & NMI to all CorePacs Assert NMI to CorePac0 Assert NMI to CorePac1 Assert NMI to CorePac2 Assert NMI to CorePac3 Assert NMI to all CorePacs End of Table 7-46 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 178: External Interrupts Electrical Data/Timing

    Pulsewidth - LRESETNMIEN low width 12*P End of Table 7-47 1 P = 1/SYSCLK1 clock frequency in ns. Figure 7-30 NMI and LRESET Timing CORESEL[3:0]/ LRESET LRESETNMIEN TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 179: Memory Protection Unit (Mpu)

    MPU registers, see the Memory Protection Unit (MPU) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page The following tables show the configuration of each MPU and the memory regions protected by each MPU.
  • Page 180 EDMA2_TC3 read EDMA2_TC3 write 36 to 37 Reserved 38 to 39 SRIO PKTDMA FFTC_A Reserved FFTC_B Reserved RAC_B_BE0 RAC_B_BE1 RAC_A_BE0 RAC_A_BE1 DebugSS EDMA3CC0 EDMA3CC1 EDMA3CC2 MSMC PCIe TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 181 (64-67) are actually used. There are two master ID values are assigned for the Queue Manager_second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses. Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 182: Mpu Registers

    Programmable range 0, end address 208h PROG0_MPPA Programmable range 0, memory page protection attributes 210h PROG1_MPSAR Programmable range 1, start address 214h PROG1_MPEAR Programmable range 1, end address TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 183 PROG15_MPSAR Programmable range 15, start address 2F4h PROG15_MPEAR Programmable range 15, end address 2F8h PROG15_MPPA Programmable range 15, memory page protection attributes 300h FLTADDRR Fault address Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 184 Programmable range 0, start address 204h PROG0_MPEAR Programmable range 0, end address 208h PROG0_MPPA Programmable range 0, memory page protection attributes 210h PROG1_MPSAR Programmable range 1, start address TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 185 Programmable range 14, memory page protection attributes 2F0h PROG15_MPSAR Programmable range 15, start address 2F4h PROG15_MPEAR Programmable range 15, end address 2F8h PROG15_MPPA Programmable range 15, memory page protection attributes Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 186 Programmable range 1, end address 218h PROG1_MPPA Programmable range 1, memory page protection attributes 300h FLTADDRR Fault address 304h FLTSTAT Fault status 308h FLTCLR Fault clear End of Table 7-56 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 187: Figure 7-31 Configuration Register (Config)

    MPU0 R-16 R-16 MPU1 R-16 Reset Values MPU2 R-16 R-16 MPU3 R-16 MPU4 R-16 MPU5 R-16 Legend: R = Read only; -n = value after reset Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 188 Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not. 0 = Assume disallowed 1 = Assume allowed TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 189: Mpu Programmable Range Registers

    0x02A6_C000 PROG9_MPSAR 0x0233_0000 0x02A6_E000 PROG10_MPSAR 0x0235_0000 0x02A8_0000 PROG11_MPSAR 0x0240_0000 0x02A9_0000 PROG12_MPSAR 0x0250_0000 0x02AA_0000 PROG13_MPSAR 0x0253_0000 0x02AA_8000 PROG14_MPSAR 0x0260_0000 0x02AB_0000 PROG15_MPSAR 0x0262_0000 0x02AB_8000 End of Table 7-60 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 190: Table 7-61 Programmable Range N End Address Register Field Descriptions

    0x02A6_DFFF PROG9_MPEAR 0x0233_03FF 0x02A6_FFFF PROG10_MPEAR 0x0235_0FFF 0x02A8_FFFF PROG11_MPEAR 0x024B_3FFF 0x02A9_FFFF PROG12_MPEAR 0x0252_03FF 0x02AA_7FFF PROG13_MPEAR 0x0254_03FF 0x02AA_FFFF PROG14_MPEAR 0x0260_FFFF 0x02AB_7FFF PROG15_MPEAR 0x0262_07FF 0x02AB_FFFF End of Table 7-62 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 191: Table 7-63 Programmable Range N Memory Protection Page Attribute Register Field Descriptions

    Controls access from ID = 6 0 = Access denied 1 = Access granted AID5 Controls access from ID = 5 0 = Access denied 1 = Access granted Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...
  • Page 192 User Write permission 0 = Access not allowed 1 = Access allowed User Execute permission 0 = Access not allowed 1 = Access allowed End of Table 7-631 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 193: Table 7-64 Programmable Range N Memory Protection Page Attribute Register (Progn_Mppa) Reset Values

    0X03FF_FCB4 0X0003_FCA4 Register 11 0X03FF_FCB6 0X0003_FCB4 Register 12 0X03FF_FCB4 0X0003_FCB4 Register 13 0X03FF_FCB6 0X0003_FCB4 Register 14 0X03FF_FCB4 0X0003_FCB4 Register 15 0X03FF_FCB4 0X0003_FCB6 End of Table 7-64 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 194: Ddr3 Memory Controller

    7.11 DDR3 Memory Controller The 64-bit DDR3 Memory Controller bus of the TMS320C6670 is used to interface to JEDEC standard-compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus with any other types of peripherals.

  • Page 195: Ddr3 Memory Controller Electrical Data/Timing

    External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the SoC through the I C module. 7.12.1 I C Device-Specific Information The TMS320C6670 device includes an I C peripheral module. NOTE: when using the I C module, ensure there are external pullup resistors on the SDA and SCL pins. The I C modules on the C6670 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may...

  • Page 196: I 2 C Peripheral Register Description(S)

    0253 0024 ICMDR C Mode Register 0253 0028 ICIVR C Interrupt Vector Register 0253 002C ICEMDR C Extended Mode Register 0253 0030 ICPSC C Prescaler Register TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 197 C Peripheral Identification Register 1 [value: 0x0000 0105] 0253 0038 ICPID2 C Peripheral Identification Register 2 [value: 0x0000 0005] 0253 003C -0253 007F Reserved End of Table 7-65 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 198: I 2 C Electrical Data/Timing

    = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 7-36 C Receive Timings Stop Start Repeated Stop Start TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 199: Table 7-67 I 2 C Switching Characteristics

    = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 7-37 C Transmit Timings Stop Start Repeated Stop Start Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 200: Spi Peripheral

    Polarity = 0 Phase = 1 toh(SPC-SIMO) Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for 0.5*tc - 2 final bit. Polarity = 1 Phase = 0 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...
  • Page 201 Minimum inactive time on SPIx_SCS\ pin between two transfers when 2*P2 - 5 SPIx_SCS\ is not held using the CSHOLD feature. End of Table 7-69 1 P2=1/SYSCLK7 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 202: Figure 7-38 Spi Master Mode Timing Diagrams — Base Timings For 3-Pin Mode

    SPI Additional Timings for 4-Pin Master Mode with Chip Select Option MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPIx_SIMO MO(0) MO(n-1) MO(n) MO(1) SPIx_SOMI MI(0) MI(1) MI(n-1) MI(n) SPIx_SCS TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 203: Hyperlink Peripheral

    7.14 HyperLink Peripheral The TMS320C6670 includes the HyperLink for companion chip/die interfaces. This is a four-lane SerDes interface designed to operate up to 12.5 Gbps per lane from pin-to-pin. The interface is used to connect with external accelerators that are manufactured using TI libraries. The Hyperbridge links must be connected with DC coupling.

  • Page 204: Figure 7-40 Hyperlink Station Management Clock Timing

    <xx> represents the interface that is being used: PM or FL Figure 7-42 HyperLink Station Management Receive Timing MCMRX<xx>CLK MCMRX<xx>DAT <xx> represents the interface that is being used: PM or FL TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 205: Uart Peripheral

    For more information on UART, see the Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Table 7-72 UART Timing Requirements...

  • Page 206: Pcie Peripheral

    Start 7.16 PCIe Peripheral The 2-lane PCI express (PCIe) module on TMS320C6670 provides an interface between the SoC and other PCIe-compliant devices. The PCI express module provides low pin-count, high-reliability, and high-speed data transfer at rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas...

  • Page 207: Security Accelerator

    2.9 ‘‘Related Documentation from Texas Instruments’’ on page 7.19 Gigabit Ethernet (GbE) Switch Subsystem The gigabit Ethernet (GbE) switch subsystem provide an efficient interface between the TMS320C6670 SoC and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.

  • Page 208: Figure 7-49 Rftclk Select Register (Cpts_Rftclk_Sel)

    Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66 for the register address and other details about the time synchronization module. The register CPTS_RFTCLK_SEL for reference clock selection of time synchronization...

  • Page 209: Management Data Input/Output (Mdio)

    The module is designed to allow almost transparent operation of the MDIO interface, with very little attention from the CorePac. For more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Table 7-77 MDIO Timing Requirements...

  • Page 210: Timers

    7.21.1 Timers Device-Specific Information The TMS320C6670 device has eight 64-bit timers in total. Of which Timer0 through Timer3 are dedicated to each of the four CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of other four timers can also be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two separate 32-bit timers.

  • Page 211: Rake Search Accelerator (Rsa)

    CPU clock divided-by-3, the TCP3e is capable of processing data channels at a throughput of >200 Mbps. For more information, see the Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 212: Bit Rate Coprocessor (Bcp)

    7.28 General-Purpose Input/Output (GPIO) 7.28.1 GPIO Device-Specific Information On the TMS320C6670, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more detailed information on device/peripheral configuration and the C6670 device pin muxing, see ‘‘Device Configuration’’...

  • Page 213: Semaphore2

    Pulse duration, RP1CLK(P) high 0.4 * C1 0.6 * C1 tr(RP1CLKN) Rise time - RP1CLKN 10% to 90% 350.00 tf(RP1CLKN) Fall time - RP1CLKN 90% to 10% 350.00 Copyright 2012 Texas Instruments Incorporated TMS320C6670 Peripheral Information and Electrical Specifications Submit Documentation Feedback...

  • Page 214: Table 7-83 Aif2 Timer Module Timing Requirements

    Figure 7-55 AIF2 RP1 Frame Synchronization Burst Timing RP1CLKN RP1CLKP RP1 Frame Burst BIT N RP1FBP/N RP1 Frame Burst BIT 0 RP1 Frame Burst BIT 2 TMS320C6670 Peripheral Information and Electrical Specifications Copyright 2012 Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 215: Receive Accelerator Coprocessor (Rac)

    EXT FRAME EVENT 7.31 Receive Accelerator Coprocessor (RAC) The TMS320C6670 has two Receive Accelerator Coprocessor (RAC) subsystems. Each RAC subsystem is a receive chip-rate accelerator based on a generic correlator coprocessor (GCCP). It supports UMTS (Universal Mobile Telecommunications System) operations and assists in transferring data received from the antenna to the receive core and performs receive functions that target the W-CDMA macro bits.

  • Page 216: Transmit Accelerator Coprocessor (Tac)

    There are three fast Fourier transform coprocessors (FFTC) intended to accelerate FFT, IFFT, DFT, and IDFT operations. For more information, see the Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 7.34 Emulation Features and Capability 7.34.1 Advanced Event Triggering (AET) The device supports advanced event triggering (AET).

  • Page 217: Trace

    Trace works in real-time and does not impact the execution of the system. For more information on board design guidelines for trace advanced emulation, see the Emulation and Trace Headers Technical Reference in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 7.34.2.1 Trace Electrical Data/Timing Table 7-85...
  • Page 218 DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.

  • Page 219: A Revision History

    Added DDR3PLLCTL1 register and field description table (Page 143) Added PASSPLLCTL1 register and field descriptions (Page 146) Added the table of Power Supply to Peripheral I/O Mapping (Page 108) Marked PREDIV and POSTDIV as reserved registers (Page 131) Copyright 2012 Texas Instruments Incorporated Revision History...
  • Page 220 Corrected the address range for I2C MMRs (Page 196) Corrected Extended Temp max to 100C from 105C (Page 13) Added BWADJ field to DDR3PLLCTL (Page 143) Added BWADJ field to PASSPLLCTL (Page 146) Revision History Copyright 2012 Texas Instruments Incorporated...

  • Page 221: B Mechanical Data

    B.2 Packaging Information The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document. Copyright 2012 Texas Instruments Incorporated Mechanical Data Submit Documentation Feedback...
  • Page 222 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS320C6670ACYP2 ACTIVE FCBGA Green (RoHS SNAGCU Level-4-245C-72HR 0 to 85 TMS320C6670CYP &...
  • Page 223 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS320C6670XCYPA ACTIVE FCBGA Green (RoHS SNAGCU Level-4-245C-72HR -40 to 100 TMS320C6670XCYP & no Sb/Br) @2010 TI A1GHZ TMS320C6670XCYPA2...
  • Page 224 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
  • Page 226 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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