Texas Instruments TMS320C6000 Series Reference Manual page 391

pipeline operation 5-12
SMPY instruction 3-115 to 3-117
SMPYH instruction 3-115 to 3-117
SMPYHL instruction 3-115 to 3-117
SMPYLH instruction 3-115 to 3-117
SPDP instruction 4-71 to 4-72
SPINT instruction 4-73 to 4-74
SPTRUNC instruction 4-75 to 4-76
SSHL instruction 3-118 to 3-119
SSUB instruction 3-120
STB instruction
15-bit offset 3-126 to 3-127
register offset or 5-bit unsigned constant
offset 3-122 to 3-125
using circular addressing 3-21
STH instruction
15-bit offset 3-126 to 3-127
register offset or 5-bit unsigned constant
offset 3-122 to 3-125
using circular addressing 3-21
store address generation, syntax 3-23
store instructions
conflicts 3-18
.D-unit instruction hazards 6-35
execution block diagram 5-14, 6-41
figure of phases 5-13, 6-40
pipeline operation 5-13, 6-40
syntax for indirect addressing 3-23
using circular addressing 3-21
using linear addressing 3-21
store or load to the same memory location,
rules 5-14, 6-41
store paths 2-7
STW instruction
15-bit offset 3-126 to 3-127
register offset or 5-bit unsigned constant
offset 3-122 to 3-125
using circular addressing 3-21
SUB instruction 3-128 to 3-130
SUB2 instruction 3-135
SUBAB instruction 3-22, 3-131 to 3-132
SUBAH instruction 3-22, 3-131 to 3-132
SUBAW instruction 3-22, 3-131 to 3-132
SUBC instruction 3-133 to 3-134
SUBDP instruction 4-77 to 4-79
.L-unit instruction hazards 6-33
execution 6-49
figure of phases 6-49
pipeline operation 6-49
SUBSP instruction 4-80 to 4-82
subtract instructions
using circular addressing 3-22
using linear addressing 3-21
SUBU instruction 3-128 to 3-130
T
timers 1-9
TMS320 family
advantages 1-2
applications 1-2 to 1-3
history 1-2
overview 1-2
TMS320C62x devices
architecture 1-7 to 1-10
block diagram 1-7
features 1-5
options 1-5 to 1-6
performance 1-4
TMS320C67x devices
architecture 1-7 to 1-10
block diagram 1-7
features 1-5
options 1-5 to 1-6
performance 1-4
traps 7-27
2-cycle DP instructions
.S-unit instruction hazards 6-23
execution 6-46
figure of phases 6-46
pipeline operation 6-46
V
VelociTI architecture 1-1
VLIW (very long instruction word) architecture 1-1
X
XOR instruction 3-136 to 3-137
Z
ZERO instruction 3-138
Index
Index-9