Texas Instruments TMS320C6000 Series Reference Manual page 276

Example 5–1. Execute Packet in Figure 5–7
The pipeline operation is based on CPU cycles. A CPU cycle is the period dur-
ing which a particular execute packet is in a particular pipeline phase. CPU
cycle boundaries always occur at clock cycle boundaries.
As code flows through the pipeline phases, it is processed by different parts
of the 'C62x. Figure 5–7 shows a full pipeline with a fetch packet in every
phase of fetch. One execute packet of eight instructions is being dispatched
at the same time that a 7-instruction execute packet is in decode. The arrows
between DP and DC correspond to the functional units identified in the code
in Example 5–1.
SADD .L1
|| SADD .L2
|| SMPYH .M2X
|| SMPY .M1X
|| B .S1
|| MVK .S2
LDW .D2
|| LDW .D1
|| MV .L2X
|| SMPYH .M1
|| SMPYH .M2
|| SHR .S1
|| SHR .S2
LOOP1:
STH .D1
Phases
|| STH .D2
|| SADD .L1
|| SADD .L2
|| SMPYH .M2X
|| SMPY .M1X
|| [B1] B .S1
|| [B1] SUB .S2
LDW .D2
|| LDW .D1
|| SADD .L1
|| SADD .L2
|| SMPYH .M1
|| SMPYH .M2
|| SHR .S1
|| SHR .S2
Pipeline Operation Overview
A2,A7,A2 ; E1 Phase
B2,B7,B2
B3,A3,B2
B3,A3,A2
LOOP1
117,B1
*B4++,B3 ; DC Phase
*A4++,A3
A1,B0
A2,A2,A0
B2,B2,B10
A2,16,A5
B2,16,B5
A5,*A8++[2] ; DP, PW, and PG
B5,*B8++[2]
A2,A7.A2
B2,B7,B2
B3,A3,B2
B3,A3,A2
LOOP1
B1,1,B1
*B4++,B3 : PR and PS Phases
*A4++,A3
A0,A1,A1
B10,B0,B0
A2,A2,A0
B2,B2,B10
A2,16,A5
B2,16,B5
TMS320C62x Pipeline 5-9