Memory Considerations; Pipeline Phases Used During Memory Accesses; Program Memory Accesses Versus Data Load Accesses - Texas Instruments TMS320C6000 Series Reference Manual

Performance Considerations
6.4.3

Memory Considerations

Figure 6–29. Pipeline Phases Used During Memory Accesses
Program memory accesses use these pipeline phases
Data load accesses use these pipeline phases
Table 6–33. Program Memory Accesses Versus Data Load Accesses
6-56
The 'C67x has a memory configuration typical of a DSP, with program memory
in one physical space and data memory in another physical space. Data loads
and program fetches have the same operation in the pipeline, they just use dif-
ferent phases to complete their operations. With both data loads and program
fetches, memory accesses are broken up into multiple phases. This enables
the 'C67x to access memory at a high speed. These phases are shown in
Figure 6–29.
To understand the memory accesses, compare data loads and instruction
fetches/dispatches. The comparison is valid because data loads and program
fetches operate on internal memories of the same speed on the 'C67x and per-
form the same types of operations (listed in Table 6–33) to accommodate
those memories. Table 6–33 shows the operation of program fetches pipeline
versus the operation of a data load.
Operation
Compute address
Send address to memory
Memory read/write
Program memory: receive fetch packet at CPU boundary
Data load: receive data at CPU boundary
Program memory: send instruction to functional units
Data load: send data to register
Depending on the type of memory and the time required to complete an
access, the pipeline may stall to ensure proper coordination of data and
instructions. This is discussed in section 6.4.3.1, Memory Stalls.
PG PS PW PR
E1 E2 E3 E4
Program
Memory
Access
Phase
PG
PS
PW
PR
DP
DP
E5
Data
Load
Access
Phase
E1
E2
E3
E4
E5