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Overview of Interrupts
7.1.2.2 Interrupt Service Table Pointer Register (ISTP)
Figure 7–4. Interrupt Service Table Pointer (ISTP)
31
R, W, +0
Legend: R
Readable by the MVC instruction
W
Writeable by the MVC instruction
+0
Value is cleared at reset
Table 7–2. Interrupt Service Table Pointer (ISTP) Field Descriptions
Field
Bits
Description
Name
0–4
Set to 0 (fetch packets must be aligned on 8-word (32-byte) boundaries).
5–9
HPEINT
Highest priority enabled interrupt. This field gives the number (related bit position in the IFR)
of the highest priority interrupt (as defined in Table 7–1) that is enabled by its bit in the IER.
Thus, the ISTP can be used for manual branches to the highest priority enabled interrupt.
If no interrupt is pending and enabled, HPEINT contains the value 00000b. The corre-
sponding interrupt need not be enabled by NMIE (unless it is NMI) or by GIE.
10–31
ISTB
Interrupt service table base portion of the IST address. This field is set to 0 on reset. Thus,
upon startup the IST must reside at address 0. After reset, you can relocate the IST by writ-
ing a new value to ISTB. If relocated, the first ISFP (corresponding to RESET) is never
executed via interrupt processing, because reset sets the ISTB to 0. See Example 7–1.
7-8
The interrupt service table pointer (ISTP) register is used to locate the interrupt
service routine. One field, ISTB identifies the base portion of the address of
the IST; another field, HPEINT, identifies the specific interrupt and locates the
specific fetch packet within the IST. Figure 7–4 shows the fields of the ISTP.
Table 7–2 describes the fields and how they are used.
ISTB
10
9
HPEINT
5
4
0
0
0
R, +0
0
0
0
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