Execution Stage Length Description For Each Instruction Type - Texas Instruments TMS320C6000 Series Reference Manual

6.2 Pipeline Execution of Instruction Types
Table 6–2. Execution Stage Length Description for Each Instruction Type
Single Cycle
Execution E1 Compute result
phases and write to
register
E2
E3
E4
E5
E6
E7
E8
E9
E10
Delay slots
Functional
unit latency
† See sections 6.3.7 (page 6-40) and 6.3.8 (page 6-42) for more information on execution and delay slots for stores and loads.
‡ See section 6.3.9 (page 6-44) for more information on branches.
Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false,
the instruction does not write any results or have any pipeline operation after E1.
2) NOP is not shown and has no operation in any of the execution phases.
The pipeline operation of the 'C67x instructions can be categorized into four-
teen instruction types. Thirteen of these are shown in Table 6–2 (NOP is not
included in the table), which is a mapping of operations occurring in each
execution phase for the different instruction types. The delay slots and func-
tional unit latency associated with each instruction type are listed in the bottom
row.
16 16 Multiply
Read operands
and start
computations
Compute result
and write to
register
0 1
1 1
Pipeline Execution of Instruction Types
Instruction Type
Store Load
Compute Compute
address address
Send address Send address to
and data to memory
memory
Access memory Access memory
Send data back
to CPU
Write data into
register
†
0
1
TMS320C67x Pipeline
Branch
Target code
‡
in PG
† ‡
4 5
1 1
6-13