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Renesas HS0005KCU04HE User Manual page 33

Multi-core emulator

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The following items will be displayed, according to the device to be debugged.
For specifications of the individual products, refer to the additional document, Supplementary
Information on Using the SHxxxx, or the online help.
• PTR: The trace-buffer pointer (+0 from the last instruction to have been executed)
• IP: Indicates the number of cycles that have elapsed since the latest trace information was
gathered. For branch instructions, the branch source and destination are counted together as
one.
• Master: Type of bus master that accessed the memory.
• Type: Displays the type of trace acquisition information.
• Branch Type: Branch type (only displayed for a branch trace)
For an AUD trace, this item is only displayed if the PPC option has been enabled.
• Bus: Displays which bus was accessed.
• R/W: Displays whether the access involved reading or writing.
• Address: Displays the addresses from which the trace data was acquired.
• Data: Displays the data acquired in the trace.
• PPC: Output from a performance counter
• Instruction, Source, Label: Displays the mnemonic of the instruction at the trace acquisition
address, along with the corresponding source code and label information. Double-clicking on
the [Source] column moves the cursor to the corresponding position in the [Editor] window.
The Type, BUS, R/W, Address, and Data columns have different meanings according to the type
of AUD trace that has been selected.
Section 2 Emulator Functions
Rev. 1.00 Nov. 26, 2007 Page 13 of 230
REJ10J1766-0100

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