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Section 5 Debugging
[Master]
[Type]
[Branch Type]
[Bus]
[R/W]
[Address]
[Data]
[Size]
[Instruction]
[Timestamp]
[Source]
[Label]
Rev. 1.00 Nov. 26, 2007 Page 110 of 230
REJ10J1766-0100
Master device that generated the event:
CPU: CPU0 was the master
Type of the trace information:
BRANCH: Branch source
DESTINATION: Branch destination
MEMORY: Memory access
S_TRACE: Executed Trace(x) function
LOST: Lost trace information (only in the realtime mode)
CPU-WAIT: CPU was waiting for the output of the trace information
(only in the non-realtime mode)
Type of the branch:
GENERAL: General branch
SUBROUTINE: Subroutine branch
EXCEPTION: Exception branch
Display the access type of the cycle:
M-Bus: M bus
I-Bus: I bus
Display whether access to data is reading or writing
READ: Read access
WRITE: Write access
Instruction address (AUD trace: If there is no base address in the trace buffer,
display the difference only)
Display the data value.
Display the size of access:
BYTE: Byte
WORD: Word
LONG: Longword
Instruction mnemonic
No timestamp, value is fixed to 0
The C/C++ or assembly-language source program
Label information
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Troubleshooting
