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Section 5 Debugging
[IP]
[CPU ID]
[Master]
[Type]
[Branch Type]
[Bus]
[R/W]
[Address]
[Data]
Rev. 1.00 Nov. 26, 2007 Page 108 of 230
REJ10J1766-0100
The amount of acquired trace information
Type of the CPU core:
CPU0: Trace is made for CPU0
CPU1: Trace is made for CPU1
Master device that generated the event.
CPU: CPU0 was the master.
DMA: The DMAC was the master.
Type of the trace information
BRANCH: Branch source
DESTINATION: Branch destination
MEMORY: Memory access
PC-RELATIVE: PC-relative access
INSTRUCTION: Instruction fetching from the external space
S_TRACE: Indicates execution of the Trace (x) function
OPERAND PRE-FETCH: Execution of the PREF instruction.
Type of the branch:
GENERAL: General branch
SUBROUTINE: Subroutine branch
EXCEPTION: Exception branch
Display the access type of the cycle:
F-Bus: F bus
M-Bus: M bus
I-Bus: I bus
DMA: Direct memory access
Display whether access to data is reading or writing
READ: Read access
WRITE: Write access
Instruction address
Display the data value
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