Renesas SuperH E10A-USB Series User Manual
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Renesas SuperH E10A-USB Series User Manual

Renesas SuperH E10A-USB Series User Manual

Renesas microcomputer development environment system superh family / sh7750 series e10a-usb for sh7760 hs7760kcu01he
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REJ10B0120-0200
SuperH™ Family E10A-USB Emulator
Additional Document for User's Manual
Supplementary Information on Using the SH7760
Renesas Microcomputer Development Environment System
SuperH™ Family / SH7750 Series
E10A-USB for SH7760 HS7760KCU01HE
Rev.2.00
Revision Date: Mar. 19, 2007

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  • Page 1 REJ10B0120-0200 SuperH™ Family E10A-USB Emulator Additional Document for User’s Manual Supplementary Information on Using the SH7760 Renesas Microcomputer Development Environment System SuperH™ Family / SH7750 Series E10A-USB for SH7760 HS7760KCU01HE Rev.2.00 Revision Date: Mar. 19, 2007...
  • Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.

  • Page 5: Table Of Contents

    Contents Section 1 Connecting the Emulator with the User System ........1 Components of the Emulator .................... 1 Connecting the E10A-USB Emulator with the User System ..........2 Installing the H-UDI Port Connector on the User System ..........3 Pin Assignments of the H-UDI Port Connector ..............3 Recommended Circuit between the H-UDI Port Connector and the MPU.......

  • Page 7: Section 1 Connecting The Emulator With The User System

    Section 1 Connecting the Emulator with the User System Components of the Emulator The E10A-USB emulator supports the SH7760. Table 1.1 lists the components of the emulator. Table 1.1 Components of the Emulator Classi- Quan- fication Component Appearance tity Remarks Hard- Emulator box HS0005KCU01H:...

  • Page 8: Connecting The E10A-Usb Emulator With The User System

    Connecting the E10A-USB Emulator with the User System To connect the E10A-USB emulator (hereinafter referred to as the emulator), the H-UDI port connector must be installed on the user system to connect the user system interface cable. When designing the user system, refer to the recommended circuit between the H-UDI port connector and the MCU.

  • Page 9: Installing The H-Udi Port Connector On The User System

    Installing the H-UDI Port Connector on the User System Table 1.3 shows the recommended H-UDI port connectors for the emulator. Table 1.3 Recommended H-UDI Port Connectors Connector Type Number Manufacturer Specifications 36-pin connector DX10M-36S Hirose Electric Co., Ltd. Screw type DX10M-36SE, Lock-pin type DX10G1M-36SE...
  • Page 10 Input/ Input/ SH7760 SH7760 Signal Signal Note Note Output Output Pin No. Pin No. AUDCK Output Input H19, P19 AUDATA0 Output /TRST Input K19, T19 (GND) AUDATA1 Output K20, T20 Input AUDATA2 Output Output J19, R19 AUDATA3 Output /ASEBRK J20, R20 BRKACK Output H20, P20...
  • Page 11 Input/ SH7760 Pin No. Pin No. Signal Output* Input /TRST Input Output /ASEBRK BRKACK Input Input /RESETP N.C. UVCC Output 10, 12, and 13 Output Notes: 1. Input to or output from the user system. 2. The slash (/) means that the signal is active-low. 3.

  • Page 12: Recommended Circuit Between The H-Udi Port Connector And The Mpu

    Recommended Circuit between the H-UDI Port Connector and the 1.5.1 Recommended Circuit (36-Pin Type) Figure 1.3 shows a recommended circuit for connection between the H-UDI and AUD port connectors (36 pins) and the MPU when the emulator is in use. Figure 1.4 shows a circuit for connection when UVCC is not connected.

  • Page 13: Gnd Audata2

    When the circuit is connected as shown in figure 1.3, the switches of the emulator are set as SW2 = 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. VccQ = 3.3 V (I/O power supply) Pulled-up at 4.7 kΩ...
  • Page 14 When the circuit is connected as shown in figure 1.4, the switches of the emulator are set as SW2 = 0 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. VccQ = 3.3 V (I/O power supply) Pulled-up at 4.7 kΩ...
  • Page 15 Note: When UVCC is not connected and the user system is turned off, note that the leakage current flows from the emulator to the user system.

  • Page 16: Recommended Circuit (14-Pin Type)

    1.5.2 Recommended Circuit (14-Pin Type) Figure 1.5 shows a recommended circuit for connection between the H-UDI and AUD port connectors (14 pins) and the MPU when the emulator is in use. Figure 1.6 shows a circuit for connection when UVCC is not connected. Notes: 1.

  • Page 17: Gnd Asebrkak

    When the circuit is connected as shown in figure 1.5, the switches of the emulator are set as SW2 = 1 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. VccQ = 3.3 V (I/O power supply) Pulled-up at 4.7 kΩ...
  • Page 18 When the circuit is connected as shown in figure 1.6, the switches of the emulator are set as SW2 = 0 and SW3 = 1. For details, refer to section 3.8, Setting the DIP Switches, in the SuperH Family E10A-USB Emulator User’s Manual. VccQ = 3.3 V (I/O power supply) Pulled-up at 4.7 kΩ...

  • Page 19: Section 2 Specifications Of The Software When Using The Sh7760

    Section 2 Specifications of the Software when Using the SH7760 Differences between the SH7760 and the Emulator 1. When the emulator system is initiated, it initializes the general registers and part of the control registers as shown in table 2.1. When the emulator is initiated from the workspace, a value to be entered is saved in a session.
  • Page 20 3. Low-Power States (Sleep, Standby, and Module Standby) For low-power consumption, the SH7760 has sleep, standby, and module standby modes. The sleep and standby modes are switched using the SLEEP instruction. When the emulator is used, the sleep and standby modes can be cleared by either normal clearing or with the [STOP] button.
  • Page 21 The stopping time of the user program is as follows: Environment: ® Host computer: 1 GHz (Pentium III) ® OS: Windows 2000 SH7760: 200 MHz (CPU clock) JTAG clock: 20 MHz When a one-byte memory is read from the command-line window, the stopping time will be about 8 ms.
  • Page 22 Table 2.2 Setting the Pin Function Controller Register Name Address Set Value PACR H’FE400000 H’0000 (initial value) PKCR H’FE400024 H’0000 (initial value) IPSELR H’FE400034 Set bit 12 or bit 13 to 1. If the above settings have not been performed, the AUD trace cannot be acquired. 11.
  • Page 23 • The internal I/O registers can be accessed from the [IO] window. However, note the following when accessing the SDMR register of the bus-state controller. Before accessing the SDMR register, specify addresses to be accessed in the I/O-register definition file (SH7760.IO) and then activate the High-performance Embedded Workshop.

  • Page 24: Specific Functions For The Emulator When Using The Sh7760

    Specific Functions for the Emulator when Using the SH7760 2.2.1 Break Condition Functions In addition to BREAKPOINT functions, the emulator has Break Condition functions. Eight types of conditions can be set (Break Condition 1,2,3,4,5,6,7,8). Break Condition 5,6 use the user break controller (UBC).
  • Page 25 Table 2.5 lists the combinations of conditions that can be set under Break Condition 1, 2, 3, 4, 5, 6, 7, 8. Table 2.5 Dialog Boxes for Setting Break Conditions Dialog Box [Break [Break [Break [Break Condition 1,5] Condition 2,3, Condition 7] Condition 8] Dialog Box...

  • Page 26: Trace Functions

    The emulator has sequential break functions. Table 2.6 lists the sequential break conditions. Table 2.6 Sequential Break Conditions Break Condition Description Sequential break condition 2-1 Program is halted when Break Condition 2 and Break Condition 1 are satisfied in that order. Break Condition 2,1 should be set.
  • Page 27 Table 2.8 shows the type numbers that the AUD function can be used. Table 2.8 Type Number and AUD Function Type Number AUD Function HS0005KCU01H Not supported HS0005KCU02H Supported AUD Trace Functions: This function is operational when the AUD pin of the device is connected to the emulator.
  • Page 28 To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace acquisition mode can be set in the [AUD mode1] or [AUD mode2] group box in the [Trace mode] page of the [Acquisition] dialog box.
  • Page 29 (a) Branch Trace Function The branch source and destination addresses and their source lines are displayed. Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function] group box of the [Trace mode] page. (b) Window Trace Function Memory access in the specified range can be acquired by trace.
  • Page 30 (c) Software Trace Function Note: This function can be supported with SHC compiler (manufactured by Renesas Technology Corp.; including OEM and bundle products) V6.0 or later. When a specific instruction is executed, the PC value at execution and the contents of one general register are acquired by trace.
  • Page 31 Internal Trace Function: This function is activated by selecting the [Internal trace] radio button in the [Trace type] group box of the [Trace mode] page. See figure 2.1, [Trace mode] Page. The internal trace functions are also activated by selecting each check box on the [Branch trace] page. Figure 2.3 [Branch trace] Page...
  • Page 32 Table 2.10 shows the internal trace functions. Table 2.10 Internal Trace Functions Function Description Branch instruction trace Traces and displays the branch instructions. The branch source address and branch destination address for the eight latest branch instructions are displayed. There are three kinds of branch instruction trace: •...
  • Page 33 Table 2.10 Internal Trace Functions (cont) Function Description Internal I/O trace Traces and displays the address and data that access the internal I/O area. To use this function, select the [Get trace information of internal I/O Area] radio button in the [Break Condition 7] dialog box and the [Acquire continuous trace] check box in the [Branch trace] page.

  • Page 34: Notes On Using The Jtag Clock (Tck) And Aud Clock (Audck)

    9. When the [Acquire continuous trace] check box is selected, and when either the [Get trace information of internal I/O area] radio button (internal I/O trace enabled) or the [Get trace information of LDTLB instruction] radio button is selected (LDTLB instruction trace enabled) with the [Break Condition 5] dialog box, •...
  • Page 35 7. When the [Normal] option is selected in the [Memory area] group box in the [General] page of the [Configuration] dialog, a BREAKPOINT is set to a physical address or a virtual address according to the SH7760 MMU status during command input when the VPMAP_SET command setting is disabled.

  • Page 36: Notes On Setting The [Break Condition] Dialog Box And The Breakcondition_ Set Command

    If a program is executed again without clearing the BREAKPOINT set at the address in which the TLB error occurs, a TLB error will occur again. Accordingly, clear the BREAKPOINT before execution. 11. An address (physical address) to which a BREAKPOINT is set is determined when the BREAKPOINT is set.

  • Page 37: Performance Measurement Functions

    command-line function. In this case, a break does not occur when Break Condition 1,4 are satisfied. Figure 2.5 [Event] Window 2.2.6 Performance Measurement Functions The emulator supports the performance measurement function. 1. Setting the performance measurement conditions To set the performance measurement conditions, use the [CPU Performance] dialog box and the PERFORMANCE_SET command.
  • Page 38 Figure 2.6 [CPU Performance] Dialog Box Note: For the command line syntax, refer to the online help. The emulator measures how many times the conditions of the user program specified with the performance analysis function are satisfied. For this function, two events can be measured simultaneously and the following conditions can be specified: (a) Measurement range One of the following ranges can be specified by either of measurement channels 1 and 2.
  • Page 39 In the second range, [PA-1 start point] and [PA-1 end point] are displayed on the [Action] part in the [Break condition] sheet of the [Event] window. Figure 2.7 [Event] Window ([Break condition] Sheet) In this case, break will not occur when the conditions of Break Condition 1 and Break Condition 4 are satisfied.
  • Page 40 (b) Measurement item Items are measured with [Channel 1 to 2] in the [CPU Performance] dialog box. Maximum two conditions can be specified at the same time. Table 2.11 shows the measurement items (Options in table 2.11 are parameters for <mode> of the PERFORMANCE_SET command. They are displayed for NAME in the [Performance Analysis] window).
  • Page 41 Table 2.11 Measurement Items Event Keyword Description Operand access count OAR* The number of times the operand access is performed on (read/with cache) the cacheable area when the cache is enabled (read access only). Operand access count OAW* The number of times the operand access is performed on (write/with cache) the cacheable area when the cache is enabled (write access only).
  • Page 42 Table 2.11 Measurement Items (cont) Event Keyword Description Two-instruction concurrent The number of times two instructions are issued at the execution count same time. FPU instruction execution The number of times FPU instruction is issued. count TRAPA instruction The number of times the TRAPA instruction is executed. execution count Interrupt count (normal) The number of interrupts (generally except for NMI).
  • Page 43 Table 2.12 Performance Count Conditions Event Count Condition Target Mode • Instruction cache miss Includes instruction fetch for the cache-off area count to count the number of times the instruction has not been fetched in one cycle. • When a cache miss occurs during an overrun fetch generated at exception.
  • Page 44 (c) Counting method One of the following methods can be specified by each of measurement channels 1 and 2. Counted by the CPU operating clock Counted by the ratio of the CPU operating clock to the bus clock When the above method 1 is specified, one CPU operating clock cycle is counted as one. When method 2 is specified, the count is incremented by 3, 4, 6, 8, 12, or 24, according to the clock frequency ratio (ratio of the CPU clock to the bus clock).

  • Page 45: Interrupts

    2. Displaying the measured result The measured result is displayed in the [Performance Analysis] window or the PERFORMANCE_ANALYSIS command with hexadecimal (32 bits). Note: If a performance counter overflows as a result of measurement, “********” will be displayed. 3. Initializing the measured result To initialize the measured result, select [Initialize] from the popup menu in the [Performance Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.

  • Page 46: Cpu Status Acquisition

    2.2.8 CPU Status Acquisition The emulator can display the SH7760 status during user program execution in realtime. It displays the items selected in the [Extended Monitor Configuration] dialog box in the [Extended Monitor] window during user program execution. The emulator can display the state of the moment when a command is input for the specified register through the command-line function.
  • Page 47 Table 2.13 Display Status (cont) Item Example Description SBTYPE (cont) B’1101 Bit2: Read or write cycle 0: Read cycle 1: Write cycle Bit1,0: Bus width Bit1=0, Bit0=0: 8-bit bus width Bit1=0, Bit0=1: 16-bit bus width Bit1=1, Bit0=0: 32-bit bus width Bit1=1, Bit0=1: 64-bit bus width EBTYPE B’0000000...
  • Page 48 Table 2.13 Display Status (cont) Item Example Description Condition match Displays whether the channel A condition of the UBC has flag been satisfied. When the UBC is used as a Break Condition, it displays whether Break Condition 6 has been satisfied. 0: Not satisfied 1: Satisfied Displays whether the channel B condition of the UBC has...
  • Page 49 Table 2.13 Display Status (cont) Item Example Description Condition match BC3=0 When Sequential break condition 4-3-2-1 and Sequential flag for sequential break condition 3-2-1 are selected, this bit is 1 when Break break (cont) Condition 3 has been satisfied and Break Condition 2 has not been satisfied.
  • Page 50 Figure 2.9 [Extended Monitor Configuration] Dialog Box...
  • Page 51 The items that have been selected are displayed in the [Extended Monitor] window. Figure 2.10 [Extended Monitor] Window Notes: 1. CPU status acquisition function [Condition match flag]: The Break Condition function clears the condition match flag after a break occurred. Therefore, note that there are following limitations on measurement of this function.
  • Page 53 Publication Date: Rev.1.00, March 15, 2004 Rev.2.00, March 19, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
  • Page 54 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
  • Page 56 SuperH™ Family E10A-USB Emulator Additional Document for User’s Manual Supplementary Information on Using the SH7760...

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