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4-2
Figure 4.1
LSIFC929 Functional Signal Grouping
Memory
Interface
INTA/
PCI
Interface
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
LSIFC929
ZZ
FLASHCS/
RAMCS/
MA[21:0]
MD[31:0]
MP[3:0]
ADV/
ADSC/
BWE[3:0]/
MWE[1:0]/
LIPRESET/
MOE[1:0]/
MCLK
AD[63:0]
GNT/
BYPASS0/
C_BE[7:0]/
BYPASS1/
FRAME/
TRDY/
STOP/
MODDEF0[2:0]
SERR/
MODDEF1[2:0]
INTB/
RST/
REQ/
IDSEL
IRDY/
DEVSEL/
TMS_CHIP
PERR/
PAR
REQ64/
PROC_DRVLS
ACK64/
PAR64
TESTRESET/
PCICLK
MODE[7:0]
ENUM/
ROMSIZE[1:0]
64EN/
FSELZ[1:0]
SWITCH
HOTSWAPEN/
TX0+
TX0−
TX1+
TX1−
RX0+
RX0−
RX1+
RX1−
RTRIM
FAULT0/
FAULT1/
ODIS0
ODIS1
RXLOS0
RXLOS1
REFCLK/
TCK
TRST/
TDI
TDO
TMS_ICE
IDDTN
ARMEN/
ZCLK
GPIO[3:0]
LED[4:0]/
SCL
SDA
Fibre Channel
Interface
JTAG and
Core Debug
Configuration
and
Miscellaneous
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