Interrupt Handling - LSI LSI53C875A Technical Manual

Pci to ultra scsi controller
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2.2.16 Interrupt Handling

2.2.16.1 Polling and Hardware Interrupts
2.2.16.2 Registers
Ultra SCSI Enable bit,
Setting this bit enables Ultra SCSI synchronous transfers in systems
that use the internal SCSI clock quadrupler.
TolerANT Enable bit,
negation must be enabled for the LSI53C875A to perform Ultra SCSI
transfers.
The SCRIPTS processors in the LSI53C875A perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C875A.
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C875A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
The registers in the LSI53C875A that are used for detecting or defining
interrupts are
Interrupt Status Zero
(ISTAT1),
Mailbox Zero
Status Zero
(SIST0),
(DSTAT),
SCSI Interrupt Enable Zero
One
(SIEN1),
DMA Control
ISTAT – The ISTAT register includes the
Interrupt Status One
One (MBOX1)
registers. It is the only register that can be accessed as a
slave during the SCRIPTS operation. Therefore, it is the register that is
SCSI Functional Description
SCSI Control Three (SCNTL3)
SCSI Test Three (STEST3)
(ISTAT0),
(MBOX0),
Mailbox One
SCSI Interrupt Status One
(SIEN0),
(DCNTL), and
(ISTAT1),
Chip Test Zero
register bit 7.
register bit 7. Active
Interrupt Status One
(MBOX1),
SCSI Interrupt
(SIST1),
DMA Status
SCSI Interrupt Enable
DMA Interrupt Enable
Interrupt Status Zero
(CTEST0), and
(DIEN).
(ISTAT0),
Mailbox
2-37

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