Miscellaneous Signals - LSI LSIFC929 Technical Manual

Table 4.5

Miscellaneous Signals

Signal I/O
GPIO[3:0] I/O
LED[4:0]/ O
SCL O
SDA I/O
ZCLK I
4-14
BGA Pad
Number Pad Type Description
A4, C5, D5, B5 3.3 V
BiDir
8 mA
w/pullup
C8, B8, A8, C9, 3.3 V
B9 BiDir
8 mA
B11 3.3 V
4 mA
BiDir
w/pullup
B12 3.3 V
4 mA
BiDir
w/pullup
B3 3.3 V
Schmitt
Input
Signal Descriptions
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
General Purpose I/O Pins. These pins default
to input mode on reset. These signals are
controlled/observed by firmware and may be
configured as inputs or outputs. GPIO[3] may
be optionally enabled as an external interrupt
source to the ARM RISC Processor core. See
also the description of the GPIO[2] pin in
Table 4.1, page 4-7, for additional information
regarding other operational capabilities of this
signal.
These output signals may be controlled by
firmware or driven by chip activity. When
configured as activity driven, the LED[n]
outputs have the following meaning when
asserted LOW:
LED[4]: Channel 1 – Fault
LED[3]: Channel 1 – Active
LED[2]: Channel 0 – Fault
LED[1]: Channel 0 – Active
LED[0]: Firmware controlled (Heartbeat)
Serial EEPROM clock.
Serial EEPROM data.
External ZBus reference clock. Based on the
table below, this input pin provides the
reference timing for the internal ZBus, IOP and
CtxMgr processors, and memory interface.
When FSELZ[1] is high, the internal ZClk tree
is sourced directly from the ZCLK input signal.
FSELZ[1:0] Internal ZClk
00 REFCLK/2
01 REFCLK * 2/3
10 External ZCLK
11 External ZCLK