Keithley 2601 Reference Manual page 359

Series 2600 System SourceMeter® Instruments Reference Manual
Reads condition, enable, event, NTR and PTR registers:
Usage
quesreg = status.questionable.unstable_output.condition
quesreg = status.questionable.unstable_output.enable
quesreg = status.questionable.unstable_output.event
quesreg = status.questionable.unstable_output.ntr
quesreg = status.questionable.unstable_output.ptr
Writes to enable, NTR and PTR registers:
status.questionable.unstable_output.enable = quesreg
status.questionable.unstable_output.ntr = quesreg
status.questionable.unstable_output.ptr = quesreg
Set operreg to one of the following values:
0
status.questionable.unstable_output.SMUA
status.questionable.unstable_output.SMUB
quesreg
To set bit B1 (SMUA), set
To set bit B2 (SMUB), set
To set both bits, set quesreg to the sum of the decimal weights of both bits.
To set bits B1 and B2, set quesreg to 6 (2 + 4).
Remarks • This attribute is used to read or write to the
• Reading a status register returns a value. The binary equivalent of the returned value
indicates which register bits are set. The least significant bit of the binary number is bit 0,
and the most significant bit is bit 15.
• For example, assume value 6 is returned for the enable register. The binary equivalent is
0000000000000110. This value indicates that bit B1 (SMUA) and bit B2 (SMUB) are set.
• The used bits of the
Bit B1, SMUA – Set bit indicates the enabled UO bit for the SMU A questionable
•
register is set.
Bit B2, SMUB – Set bit indicates the enabled UO bit for the SMU B questionable
•
register is set.
Details See "status.operation.user.condition =
Example Sets the SMUA bit of the questionable unstable output enable register:
status.questionable.unstable_output.enable =
status.questionable.unstable_output.SMUA
2600S-901-01 Rev. C / January 2008
can also be set to the decimal weight of the bit to be set. Examples:
quesreg
quesreg
questionable
instrument registers are described as follows:
Return to Section Topics
Clears all bits.
Sets SMUA bit (B1).
Sets SMUB (B2).
1
to 2 (2 ).
2
to 4 (2 ).
questionable
unstable output registers.
2" in Appendix
Section 12: Instrument Control Library
D.
12-99