Fec Crc And Transmit Frame Control Word Register (Fecctcwr) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
31–26 —
25 SW_RST
24 RST_CTL
23–0 —

30.3.3.35 FEC CRC and Transmit Frame Control Word Register (FECCTCWR)

The FEC can be sent a control word (32-bit) with additional instructions on how to transmit the current
frame. This control word instructs the FEC to append or not append a CRC value to the frame being
transmitted. Control of the transmit frame control word and its contents are provided in this register.
31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg
Addr
Figure 30-38. FEC CRC and Transmit Frame Control Word Register (FECCTCWR)
Bits Name
31–26 —
25 CRC
24 TFCW
23–0 —
30-42
Table 30-41. FECFRST Field Descriptions
Reserved, should be cleared
Software Reset. This bit controls the soft reset of the FEC FIFOs. A soft reset will reset the
FIFO pointers and byte counters but notthe status and control registers. To cause a soft
reset this bit should be set and then cleared by application software.
Reset control. Setting this bit allows the FEC controller to perform a soft reset of the FIFOs
when the FEC is disabled (ECR[ETHER_EN] cleared).
Reserved, should be cleared
28 27 26 25
0 0 0 CRC TFCW
0 0 0 0
12 11 10 9
0 0 0 0
0 0 0 0
MBAR + 0x91C8 (FEC0), 0x99C8 (FEC1)
Table 30-42. FECCTCWR Field Descriptions
Reserved, should be cleared
CRC enable. This bit is associated with the TC field in FEC's Transmit Frame Control Word.
A 1 in this bit location translates to TC = 1 and instructs FEC to append CRC to the current
transmit frame.
Transmit frame control word enable. This bit controls whether a "control word" is appended
to the frame being transferred to the transmit FIFO.
Reserved, should be cleared
MCF548x Reference Manual, Rev. 3
Descriptions
24 23 22 21
0 0 0
0 0 0 0
8 7 6 5
0 0 0 0
0 0 0 0
Descriptions
20 19 18 17
0 0 0 0
0 0 0 0
4 3 2 1
0 0 0 0
0 0 0 0
Freescale Semiconductor
16
0
0
0
0
0