Memory Maps; Overview; Default Processor Memory Map; Table 8-1 Default Processor Memory Map - Motorola CPCI-6115 Installation And Use Manual

Memory Maps

8.1

Overview

This chapter supplies information for use of the CPCI-6115 family of Single Board Computers
in a system configuration. Here you will find descriptions of the memory maps and software
initialization.
8.2 Memory Maps
There are three points of view for memory maps:
Mapping of all resources as viewed by the processor (MPU bus memory map)
Mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map)
Mapping of onboard resources as viewed by the CompactPCI bus
The following sections give a general description of the CPCI-6115 memory organization from
the above three points of view. Detailed memory maps can be found in the MCPN905
CompactPCI Single Board Computer Programmer's Reference Guide (MCPN905A/PG).
8.2.1

Default Processor Memory Map

The MV64360 presents a default CPU memory map following RESET negation. The following
table shows the default Memory Map from the point of view of the Processor. Address bits
[35:32] are only relevant for the MPC7457 extended address mode and are not shown in the
following tables.

Table 8-1 Default Processor Memory Map

Processor Address
Start
0000 0000
0080 0000
0100 0000
0180 0000
0200 0000
1000 0000
1200 0000
1400 0000
1C00 0000
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
End Size
007F FFFF 8 MB
00FF FFFF 8 MB
017F FFFF 8 MB
01FF FFFF 8 MB
0FFF FFFF 224 MB
11FF FFFF 32 MB
13FF FFFF 32 MB
1BFF FFFF 128 MB
1C7F FFFF 8 MB
Definition
DRAM Bank 0
DRAM Bank 1
DRAM Bank 2
DRAM Bank 3
Unassigned
PCI Bus 0 I/O Space
PCI Bus 0 Memory Space 0
Unassigned
Device CS0*
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