Bits 2-0 Watchdog Timer Delay; Enum Status And Control Register: Fpga Index - 11H; Enum Status And Control; Table 4-17. Watchdog Timer Delay - Motorola CPV5000 Installation And Reference Manual

Functional Description

Bits 2-0 watchdog timer delay

Bits 2 to 0 control the delay of the watchdog timer until the function bits 4 to
3 are activated.
4

ENUM status and control register: FPGA index - 11h

The ENUM status and control register is used to get the status of the ENUM-
line for hot swap enabled systems. This register is used to check the level of
the ENUM- line to check the source of the interrupt.

ENUM status and control

The level of the ENUM- line can be read at bit 0 of this register. Bits 1, 2, and
3 are read/write and can be used to store control bits. The control bits are not
defined for any particular purpose at this time.
Table 4-18. Register data port when I/O port 75h: FPGA register index port - 01h
Bit 7
Function
4-22
Table 4-17.
Watchdog timer delay
Data Watchdog count down delay
000 17.8 milliseconds
001 71.1 milliseconds
010 284 milliseconds
011 1.14 seconds
100 4.55 seconds
101 18.22 seconds
110 72.8 seconds
111 291 seconds
6 5 4
Reserved
3 2 1
Control bits
0
ENUM-