Mpc Error Status Register - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

MPC Error Status Register

Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-32
SERRI PCI System Error Interrupt Enable.When this bit is
set, the PERR bit in the MERST register will be used to
assert an interrupt through the MPIC interrupt controller.
When this bit is clear, no interrupt will be asserted.
SMAI PCI Master Signalled Master Abort Interrupt
Enable.When this bit is set, the SMA bit in the MERST
register will be used to assert an interrupt through the
MPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.
RTAI PCI Master Received Target Abort Interrupt
Enable.When this bit is set, the RTA bit in the MERST
register will be used to assert an interrupt through the
MPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.
1 1 1
0 1 2
R R
$00 $00
OVF Error Status Overflow. This bit is set when any error is
detected and any of the error status bits are already set. It
may be cleared by writing a 1 to it; writing a 0 to it has no
effect.
MATO MPC Address Bus Time-out. This bit is set when the
MPC address bus timer times out. It may be cleared by
writing it to a 1; writing it to a 0 has no effect. When the
$FEFF0024
1 1 1 1 1 1 1 2 2 2
3 4 5 6 7 8 9 0 1 2
R
$00
2 2 2 2 2 2 2 3 3
3 4 5 6 7 8 9 0 1
MERST