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68000 Motherboard User's Manual
Peripheral Name
Interrupt Enable Register,
A1CON340
Clock Synchronization
Register
On-Board Interrupt Logic Level
Hardware Entropy Generator
On-Board Digital Input Interface,
A1CON300
On-Board Output Latch,
A1CON290
7.12.1
Int errupt E nable Regist er
Ref. Des.:
A1CON340
Addr: ONBD_BASE+$A0000 (Interrupt Enable Register)
Name: ONBD_INTEN
Size: 8 bit
Reset: $00
The Interrupt Enable Register is an 8-bit register that controls the availability of the On-
Board Interrupt Logic to trigger interrupts. Bit 0 of this register is a global mask, set to 1
to disable all 7 levels of interrupt sources. Bits 1-7 are individual controls for each of the
7 interrupt levels, organized respectively.
interrupt level is available for trigger. When an interrupt occurs, this bit must be cleared
by software to reset the interrupt logic for that interrupt level. It may then be restored to
1 to resume triggering at that interrupt level. For deeper detail, see section 7.13, Interrupt
Logic, below.
7.12.2
The Clock Sync hronization Register
Addr: ONBD_BASE+$C0000 (Clock Synchronization Register)
Name: ONBD_SYNC
Size: 8 bit
External events to the system clock are synchronized through the Clock Synchronization
Register.
However, this register does not synchronize asynchronous transitions of
Table 14: On-Board Register Summary
ONBD_BASE
+offset
+$A0000
+$C0000
+$E0000
Page 33 of 54
Quick Description
1
0-7
$00 Interrupt Logic control
1
Input signals
synchronized to clock
0-2
$07 On-Board Interrupt
Logic Level
3
XX Hardware Entropy
Generator Bit
4-7
XX On-Board Digital Input
Interface
1
0-7
$00 Discrete digital output
signal latch
With its bit set to 1, the corresponding
Rev. A
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