Ppc Error Status Register - Motorola MTX Series Programmer's Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller
2

PPC Error Status Register

Address
Bit
Name
Operation
Reset
2-28
PERRI PCI Parity Error Interrupt Enable.When this bit is set, the
PERR bit in the ERRST register will be used to assert an interrupt through
the OpenPIC interrupt controller. When this bit is clear, no interrupt will
be asserted.
SERRI PCI System Error Interrupt Enable.When this bit is set, the
PERR bit in the ERRST register will be used to assert an interrupt through
the OpenPIC interrupt controller. When this bit is clear, no interrupt will
be asserted.
SMAI PCI Master Signalled Master Abort Interrupt Enable.When
this bit is set, the SMA bit in the ERRST register will be used to assert an
interrupt through the OpenPIC interrupt controller. When this bit is clear,
no interrupt will be asserted.
RTAI PCI Master Received Target Abort Interrupt Enable.When this
bit is set, the RTA bit in the ERRST register will be used to assert an
interrupt through the OpenPIC interrupt controller. When this bit is clear,
no interrupt will be asserted.
$FEFF0024
0 1 2 3 4 5 6 7 8 9
R R
$00 $00
OVF Error Status Overflow. This bit is set when any error is detected
and any of the error status bits are already set. It may be cleared by writing
a 1 to it; writing a 0 to it has no effect.
1 1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8
R
$00
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1 2 2 2 2 2 2 2 2 2
9 0 1 2 3 4 5 6 7 8
ERRST
2 3 3
9 0 1