Mobile Access Interface Interrupt Outputs - Epson S1C33210 Technical Manual

Cmos 32-bit single chip microcomputer
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III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES
D. Interrupt source: Idle detect
Condition
The signal latched into the idle detect changes from "0" to "1."
To clear
Reset E/S INT command
(8)
MSINT = Modem status change interrupt
Interrupt source Change in modem status input signals
Condition
The RI, CTS, DCD, or DSR input signal changes (either direction).
To clear
Write "1" to the corresponding interrupt status bit

Mobile Access Interface Interrupt Outputs

The five mobile access interface interrupt groups (UINT4 to UINT0) are connected to the CPU through port
interrupt request output pins (CP4 to CP0). The communications block interrupt select register provides settings for
mapping all five to a single output, or, at the other extreme, to distribute them to separate outputs.
Interrupt Group Assignments for Communications Modes
The communications macro select (MCRS) register (D[1:0]/0x200000) specifies the communications mode and
thus the assignments to the five interface interrupt groups UINT4 to UINT0.
Communications
mode
Interrupt
UINT0
Group
UINT1
UINT2
UINT3
UINT4
Interrupt Request Outputs CP[4:0]
The communications block CPx interrupt select registers (CPxEN) (D[4:0]/0x0200020 to D[4:0]/0x0200028)
provide program control over the mapping of the five interface interrupt groups UINT4 to UINT0 to the
interrupt request pins CP4 to CP0 using the following formulas.
CP0 = CP0EN0*UINT0 + CP0EN1*UINT1 + CP0EN2*UINT2 + CP0EN3*UINT3 + CP0EN4*UINT4
CP1 = CP1EN0*UINT0 + CP1EN1*UINT1 + CP1EN2*UINT2 + CP1EN3*UINT3 + CP1EN4*UINT4
CP2 = CP2EN0*UINT0 + CP2EN1*UINT1 + CP2EN2*UINT2 + CP2EN3*UINT3 + CP2EN4*UINT4
CP3 = CP3EN0*UINT0 + CP3EN1*UINT1 + CP3EN2*UINT2 + CP3EN3*UINT3 + CP3EN4*UINT4
CP4 = CP4EN0*UINT0 + CP4EN1*UINT1 + CP4EN2*UINT2 + CP4EN3*UINT3 + CP4EN4*UINT4
Port Interrupts and Interrupt Request Outputs
Table 10.10 summarizes the relationships between the above interrupt request outputs CP[4:0] and the port
input interrupts FPT[7:3].
B-III-10-20
Table 10.9 Interrupt Groups
Serial interface
Ch. 3
communications
MSINT
MSINT
Table 10.10 Port Interrupts and Interrupt Request Outputs
Interrupt
source
11
FPT7
P27
FPT6
P26
FPT5
P25
FPT4
P24
FPT3
P23
FPT2
P22
FPT1
P21
FPT0
P20
UART
HDLC
communications
RXINT
TXINT
SPINT
ESINT
MSINT
SPT setting
10
01
P33
P32
P05
P31
P04
P03
<CP4>
P02
K52
P01
K51
P00
K50
EPSON
PDC
communications
communications
PDCINT
PRINT
PTINT
MSINT
MSINT
00
<CP3>
<CP2>
<CP1>
<CP0>
K63
K62
K61
K60
S1C33210 FUNCTION PART
PHS

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