Pdc Communications Control And Operation - Epson S1C33210 Technical Manual

III PERIPHERAL BLOCK: MONITORED MOBILE ACCESS INTERFACES

PDC Communications Control and Operation

Transmit Control
(1) Enabling transmit operation
Setting the transmit enable (TXEN) bit in the PDC command register (D1/0x0200102) to "1" enables transmit
operation, starting transmission from the start of the specified transmit buffer at the next falling edge in the PDC
frame signal.
(2) Procedure
There are two 32-byte transmit data buffers. The transmit buffer select (TXBS) bit in the PDC command
register (D2/0x0200102) specifies which one contains the data to transmit: A ("0") or B ("1").
Before enabling the transmit operation, therefore, write the transmit data to buffer A, buffer B, or both and then
specify the buffer (TXBS) in the write (0x0200102) setting the transmit enable (TXEN) bit.
For the next transmit operation, write the data to the buffer not currently in use and then switch buffers (TXBS)
in the write (0x0200102) for starting the next transmit operation. Repeat as needed.
Note that the hardware does not automatically switch buffers.
(3) Ending transmit operation
To terminate transmit operation, set the TXEN bit to "0."
Note: Failing to write the data to the buffer before the transmit operation starts or overwriting buffer
contents during a transmit operation does not trigger an underrun error, overrun error, or other
warning.
Receive Control
(1) Enabling receive operation
Setting the receive enable (RXEN) bit in the PDC command register (D0/0x0200102) to "1" enables receive
operation, starting data storage in the currently selected receive buffer at the next rising edge in the PDC frame
signal.
(2) Procedure
When the RXEN bit starts receive operation, the hardware starts converting the incoming serial data into 8-bit
parallel data and storing it in a data buffer. It also starts the CRC calculations.
When the hardware has received the 224 bits for a frame, it sets the RXBB and RXBA bits in the PDC status
register (D[1:0]/0x0200104) to indicate which buffer contains the data and automatically switches to the other
buffer.
The hardware also sets the CRCER1 and CRCER2 bits in the PDC status register (D[7:6]/0x0200104) to the
results of the CRC-16 and CRC-CCITT checks, respectively. The data remains in the buffer regardless of any
errors.
(3) Ending receive operation
To terminate receive operation, set the RXEN bit to "0."
Note: Failing to read the data from a buffer before the next receive operation for that buffer or reading from
a buffer while it is receiving data does not trigger an underrun error, overrun error, or other warning.
Interrupt Outputs
The hardware sets the PDCINT bit in the same register (D0/0x0200100) to "1" every 20 ms, at falling edges in
the PDC frame signal, regardless of the TXEN and RXEN settings in the PDC command register. If the INTE
bit in the PDC interrupt register (D1/0x0200100) is "1," this transition sends a PDC interrupt request to the
CPU. The interrupt handler then checks the PDC command register for updates and the PDC status register.
Note that the PDCINT bit remains "1" until the software writes "1" to it to clear it.
B-III-10-10
EPSON
S1C33210 FUNCTION PART