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V DMA BLOCK: HSDMA (High-Speed DMA)
Register name
Address
Bit
High-speed
0048222
DF
DMA Ch.0
(HW)
DE
control register
DD–8
Note:
D7
D) Dual address
D6
mode
D5
S) Single
D4
address
D3
mode
D2
D1
D0
High-speed
0048224
DF
DMA Ch.0
(HW)
DE
low-order
DD
source address
DC
set-up register
DB
DA
Note:
D9
D) Dual address
A8
mode
D7
S) Single
D6
address
D5
mode
D4
D3
D2
D1
D0
High-speed
0048226
DF
DMA Ch.0
(HW)
DE
high-order
DD
source address
DC
set-up register
Note:
D) Dual address
DB
mode
DA
S) Single
D9
address
A8
mode
D7
D6
D5
D4
D3
D2
D1
D0
High-speed
0048228
DF
DMA Ch.0
(HW)
DE
low-order
DD
destination
DC
address set-up
DB
register
DA
D9
Note:
A8
D) Dual address
D7
mode
D6
S) Single
D5
address
D4
mode
D3
D2
D1
D0
B-V-2-20
Name
Function
DUALM0
Ch.0 address mode selection
D0DIR
D) Invalid
S) Ch.0 transfer direction control
–
reserved
TC0_H7
Ch.0 transfer counter[15:8]
TC0_H6
(block transfer mode)
TC0_H5
TC0_H4
Ch.0 transfer counter[23:16]
TC0_H3
(single/successive transfer mode)
TC0_H2
TC0_H1
TC0_H0
S0ADRL15
D) Ch.0 source address[15:0]
S0ADRL14
S) Ch.0 memory address[15:0]
S0ADRL13
S0ADRL12
S0ADRL11
S0ADRL10
S0ADRL9
S0ADRL8
S0ADRL7
S0ADRL6
S0ADRL5
S0ADRL4
S0ADRL3
S0ADRL2
S0ADRL1
S0ADRL0
–
reserved
DATSIZE0
Ch.0 transfer data size
S0IN1
D) Ch.0 source address control
S0IN0
S) Ch.0 memory address control
S0ADRH11
D) Ch.0 source address[27:16]
S0ADRH10
S) Ch.0 memory address[27:16]
S0ADRH9
S0ADRH8
S0ADRH7
S0ADRH6
S0ADRH5
S0ADRH4
S0ADRH3
S0ADRH2
S0ADRH1
S0ADRH0
D0ADRL15
D) Ch.0 destination address[15:0]
D0ADRL14
S) Invalid
D0ADRL13
D0ADRL12
D0ADRL11
D0ADRL10
D0ADRL9
D0ADRL8
D0ADRL7
D0ADRL6
D0ADRL5
D0ADRL4
D0ADRL3
D0ADRL2
D0ADRL1
D0ADRL0
Setting
1 Dual addr
0 Single addr
–
1 Memory WR 0 Memory RD
–
–
1 Half word
0 Byte
S0IN[1:0]
Inc/dec
1
1
Inc.(no init)
1
0
Inc.(init)
0
1
Dec.(no init)
0
0
Fixed
EPSON
Init. R/W
Remarks
0
R/W
–
–
0
R/W
–
–
Undefined in read.
X
R/W
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
–
–
0
R/W
0
R/W
0
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S1C33210 FUNCTION PART
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